Network interface sharing techniques for area optimized NoC architectures

Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008

Volumn , Issue , 2008, Pages 10-17

  Ferrante, Alberto ^a   Medardoni, Simone ^a   Bertozzi, Davide ^a  

^a UNIVERSITY OF FERRARA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ARTS COMPUTING; ELECTRIC NETWORK TOPOLOGY; SYSTEMS ANALYSIS; TELECOMMUNICATION NETWORKS;

AREA EFFICIENT; BUFFERING RESOURCES; CONTROL LOGICS; INTER-CONNECTS; INTERCONNECT TECHNOLOGIES; NETWORK INTERFACES; NETWORK ON CHIPS; NOC ARCHITECTURES; ON CHIPS; OPERATING CONDITIONS; PERFORMANCE DEGRADATIONS; PRELIMINARY ANALYSIS; PROCESSOR CORES; SPEED-UPS;

ARCHITECTURAL DESIGN;

EID: 57649208766     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2008.111     Document Type: Conference Paper

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