Floorplanning driven network-on-chip synthesis for 3-D SoCs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2011, Pages 1203-1206

  Zhong, Wei ^a   Chen, Song ^a   Ma, Fei ^a   Yoshimura, Takeshi ^a   Goto, Satoshi ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FLOOR-PLANNING; FLOORPLANS; INTEGER LINEAR PROGRAMMING; NETWORK ON CHIP; NETWORK-ON-CHIPS; OPTIMAL CLUSTERING; PATH ALLOCATION; POWER-PERFORMANCE EFFICIENT; SILICON LAYER; SYSTEM ON CHIPS; TECHNOLOGY ADVANCES;

INTEGER PROGRAMMING; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); ROUTERS; THREE DIMENSIONAL; VLSI CIRCUITS;

CLUSTERING ALGORITHMS;

EID: 79960881634     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2011.5937785     Document Type: Conference Paper

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