Synthesis of networks on chips for 3D systems on chips

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2009, Pages 242-247

  Murali, Srinivasan ^a   Seiculescu, Ciprian ^a   Benini, Luca ^b   De Micheli, Giovanni ^a  

^a EPFL   (Switzerland)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

3D; Application specific; Networks on chip; Topology synthesis

Indexed keywords

3D; 3D INTERCONNECT; 3D SYSTEMS; 3D TECHNOLOGIES; APPLICATION PERFORMANCE; APPLICATION-SPECIFIC; COMPARATIVE STUDIES; DESIGN COMPLEXITY; INTERCONNECT POWER; LATENCY REDUCTIONS; MESH TOPOLOGIES; NETWORKS ON CHIP; NOC DESIGNS; POWER-EFFICIENT; POWER-PERFORMANCE EFFICIENT; SILICON LAYERS; SYNTHESIS METHODS; SYSTEMS ON CHIPS; TOPOLOGY SYNTHESIS;

APPLICATIONS; BENCHMARKING; BIOLOGICAL MATERIALS; COMPUTER AIDED DESIGN; D REGION; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CONVERTERS; ELECTRIC NETWORK TOPOLOGY; PROGRAM COMPILERS; THREE DIMENSIONAL; TOPOLOGY;

MICROPROCESSOR CHIPS;

EID: 64549114532     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2009.4796487     Document Type: Conference Paper

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