Multiple clock and voltage domains for chip multi processors

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 459-468

  Rotem, Efraim ^a   Ginosar, Ran ^b   Mendelson, Avi ^c   Weiser, Uri ^b  

^a INTEL CORPORATION   (United States)

^b TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^c MICROSOFT RESEARCH   (United States)

Author keywords

Chip multi processor; Clock domains; DVFS; Power management; Voltage domain

Indexed keywords

ANALYTICAL MODEL; CHIP MULTIPROCESSORS; CLOCK DOMAINS; CYCLE-ACCURATE SIMULATORS; DESIGN CONSIDERATIONS; DYNAMIC VOLTAGE AND FREQUENCY SCALING; FREQUENCY DOMAINS; HYBRID MODEL; MULTI CORE; MULTIPLE VOLTAGE; NUMBER OF THREADS; PHYSICAL LIMITATIONS; POWER CONSTRAINTS; POWER DELIVERY; POWER DOMAIN; POWER MANAGEMENTS; THERMAL CONSTRAINTS; TOTAL POWER; VOLTAGE DOMAINS;

CLOCKS; ELECTRIC POWER MEASUREMENT; ELECTRIC POWER TRANSMISSION; ENERGY MANAGEMENT; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS;

TOPOLOGY;

EID: 76749142049     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669170     Document Type: Conference Paper

References (23)

1. Isci, C., Buyuktosunoglu A., Cher C., Bose, P., Martonosi, M. An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. In Proceedings of 39th Annual IEEE/ACM International Symposium on Microarchitecture, 2006.
2. Ogras, U. Y., Marculescu, R., Choudhary, P., and Marculescu, D. Voltage-frequency island partitioning for GALS-based networks-on-chip. In Proceedings of the 44th Annual Design Automation Conference, June 2007, San Diego, California.
3. Bellosa, F., The benefits of event driven energy accounting in power-sensitive systems, In Proceedings of the 9th workshop on ACM SIGOPS European workshop: beyond the PC: new challenges for the operating system, September 2000, Kolding, Denmark.
4. Contreras, G., Martonosi, M. Power prediction for Intel XScale® processors using performance monitoring unit events. In Proceedings of the 2005 international symposium on Low power electronics and design, August 2005, San Diego, CA, USA
5. Kihwan C., Soma, R., Pedram, M. Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 24(1), 18-28. January 2005.
6. Hsu, C., Feng, W. Effective dynamic voltage scaling through CPU-boundedness detection. Proc. In Proceedings of 4th Workshop Power-Aware Computer Systems, December 2004.
7. Wu, Q., Martonosi, M., Clark, D.W., Reddi, V.J., Connors, D., Wu, Y., Lee, J., Brooks, D. Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance. Micro, IEEE, 26(1), 119-129. January 2006.
8. Hill, M.D., Marty, M.R. Amdahl's Law in the Multicore Era. Computer , 41(7),33-38. July 2008.
9. Annavaram, M., Grochowski, E., Shen, J. Mitigating Amdahl's law through EPI throttling. In Proceedings of the 32nd International Symposium on Computer Architecture, June 2005.
10. Grochowski, E., Ronen, R,, Shen, J., Wang. H. Best of both latency and throughput. In Proceedings of the International Conference on Computer Design, 236-243. October 2004, San Jose, CA.
11. Joseph, R., Brooks, D., Martonosi, M. Control techniques to eliminate voltage emergencies in high performance processors. In Proceedings of the 9th International Symposium on High-Performance Computer Architecture, February 2003.
12. Gupta, M. S., Oatley, J. L., Joseph, R., Wei, G.-Y., Brooks, D. Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. In Proceedings of Design, Automation, and Test in Europe Conference, April 2007.
13. Kim, W., Gupta M., Wei, G. Y., Brooks, D. System level analysis of fast, per-core DVFS using on-chip switching regulators. In Proceedings of International Symposium on High-Performance Computer Architecture, February 2008.
14. Naveh, A., Rotem, E., Mendelson, A., Gochman, S., Chabukswar, R., Krishnan, K., Kumar, A. Power and Thermal Management in the Intel Core Duo Processor. Intel Technology Journal. 10( 2). 109-122.
15. Liang, X,, Brooks, D., Wei G.-Y. A process-variationtolerant floating-point unit with voltage interpolation and variable latency. In Proceedings of International Solid-State Circuits Conference, February 2008.
16. Zane, B., Karen, R., IA Product Update, In Cebit, March 2009. http://www.intel.com/corporate/pressroom/emea/deu/cebit/pd fs/CeBIT-Client-Tech- Briefing.pdf
17. Intersil, Document Number: FN9289.3, 14 February, 2007, http://www.intersil.com/data/fn/FN9289.pdf
18. Waizman, E., Chung, C. Y. Resonant free power network design using extended adaptive voltage positioning (EAVP) methodology. IEEE Trans. Adv. Package. 24(3). 236-244, August 2001.
19. Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket, November 2006. http://www.intel.com/ assets/pdf/designguide/313214.pdf
20. Ren, Y., Yao, K., Xu, M., Lee, F.C. Analysis of the power delivery path from the 12 V VR to the microprocessor. In Proceedings of the Applied Power Electronics Conference and Exposition, 285-291. 2004
21. Advanced Configuration and Power Interface (ACPI) Specification, October 2006. http://www.acpi.info/
22. Schittkowski, K., Zillober, C., Zotemantel, R. Numerical comparison of nonlinear programming algorithms for structural optimization, Structural Optimization, 7(1), 1-19. 1994.
23. Gochman, S., Mendelson, A., Naveh, A., Rotem, E. Introduction to Intel® Core™ Duo processor architecture. Intel Technology Journal, 10(2), 2006.