NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing

ASICON 2007 - 2007 7th International Conference on ASIC Proceeding

Volumn , Issue , 2007, Pages 890-893

  Xu, Yang ^a   Zhang, Qing Li ^a   Fu, Fang Fa ^a   Yu, Ming Yan ^a   Liu, Cheng ^a  

^a HARBIN INSTITUTE OF TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER SUPPLIES TO APPARATUS; NICKEL ALLOYS; TECHNOLOGY;

ADAPTIVE ROUTING; AVERAGE LATENCY; INTERNATIONAL CONFERENCES; LOOK-UP TABLE; NETWORK INTERFACES; ON CHIPS; PACKET REORDERING; PROPOSED ARCHITECTURES;

NICKEL;

EID: 48349146464     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASIC.2007.4415774     Document Type: Conference Paper

References (6)

1. Davide Bertozzi and Luca Benini, Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip, IEEE Circuits and systems magazine, 2, p. 18-31(2004).
2. A.Radulescu, J.Dielissen, S.Pestana, "An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration," IEEE Trans. Computer-Aided Design, vol. 24, p.4-17(Jan, 2005).
3. Daewook Kim, Manho Kim and Gerald E. Sobelman, NIUGAP :Low Latency Network Interface Architecture with Gray Code for Networks-on-Chip, IEEE ISCAS, p.3902-3905 (2006).
4. Praveen Bhojwani and Rabi N. Mahapatra, Core Network Interface Architecture and Latency Constrained On-Chip Communication, Proc. of the ISQED (2006).
5. ARM, AMBA AXI Protocol Spec. (Mar, 2004).
6. A. Radulescu and K. Goossens. Communication services for networks on chip. In S. Bhattacharyya, E.Deprettere, and J.Teich, editors, Domain-Specific Embedded Multiprocessors Dekker, p. 275-297 (2003).