A reusable coverage-driven verification environment for Network-on-Chip communication in embedded system platforms

Proceedings of the 7th Workshop on Intelligent Solutions in Embedded Systems, WISES 2009

Volumn , Issue , 2009, Pages 71-77

  Vitullo, Francesco ^a   Saponara, Sergio ^a   Petri, Esa ^a   Casula, Michele ^a   Fanucci, Luca ^a   Maruccia, Giuseppe ^b   Locatelli, Riccardo ^b   Coppola, Marcello ^b  

^a UNIVERSITY OF PISA   (Italy)

^b STMicroectronics   (France)

Author keywords

E Reuse Methodology (eRM); Functional Coverage; Functional verification; Intellectual property (IP); Multi Processor System on Chip (MPSoC); Network on Chip (NoC)

Indexed keywords

E REUSE METHODOLOGY (ERM); FUNCTIONAL COVERAGE; FUNCTIONAL VERIFICATION; MULTI-PROCESSOR SYSTEM-ON-CHIP (MPSOC); NETWORK-ON-CHIP (NOC);

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; INTELLECTUAL PROPERTY; INTERNET PROTOCOLS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; REUSABILITY; SYSTEMS ANALYSIS;

EMBEDDED SYSTEMS;

EID: 70449360138     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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