Design of a high-throughput distributed shared-buffer NoC router

NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2010, Pages 69-78

  Ramanujam, Rohit Sunkam ^a   Soteriou, Vassos ^b   Lin, Bill ^a   Peh, Li Shiuan ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b CYPRUS UNIVERSITY OF TECHNOLOGY   (Cyprus)

^c Department of Electrical Engineering and Computer Science   (United States)

Author keywords

On chip interconnection networks; Router microarchitecture

Indexed keywords

HIGH LOAD; HIGH-THROUGHPUT; MICRO ARCHITECTURES; ON-CHIP INTERCONNECTION NETWORK; ON-CHIP INTERCONNECTION NETWORKS; ON-CHIP NETWORKS; PACKET LATENCIES; POWER BUDGETS; POWER OVERHEAD; QUEUING DELAY; ROUTER ARCHITECTURE; ROUTER DESIGN; SATURATION THROUGHPUT; SYNTHETIC WORKLOADS;

COMPUTER ARCHITECTURE; DESIGN; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; THROUGHPUT;

ROUTERS;

EID: 77955111275     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2010.17     Document Type: Conference Paper

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