SHAPES: A tiled scalable software hardware architecture platform for embedded systems

CODES+ISSS 2006: Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis

Volumn , Issue , 2006, Pages 167-172

  Paolucci, Pier S ^a   Jerraya, Ahmed A ^b   Leupers, Rainer ^c   Thiele, Lothar ^d   Vicini, Piero ^e  

^a INFN SEZIONE DI ROMA   (Italy)

^b TIMA LABORATORY   (France)

^c RWTH AACHEN UNIVERSITY   (Germany)

^d ETH ZURICH   (Switzerland)

^e SAPIENZA UNIVERSITY OF ROME   (Italy)

Author keywords

Application mapping; Binding; Distributed network processors; Embedded systems; Hardware dependent software; Model based design; MP SOC; Network of processes; Retargetable compiler; RISC; Scheduling; Simulation; Tiled parallel architectures; VLIW

Indexed keywords

BANDWIDTH; COMPUTER PROGRAMMING; GATEWAYS (COMPUTER NETWORKS); MICROPROCESSOR CHIPS; NANOSYSTEMS; REDUCED INSTRUCTION SET COMPUTING; SOFTWARE ARCHITECTURE; STORAGE ALLOCATION (COMPUTER); SWITCHING NETWORKS;

DISTRIBUTED NETWORK PROCESSOR; HARDWARE DEPENDENT SOFTWARE; RETARGETABLE COMPILER; TILED PARALLEL ARCHITECTURES;

EMBEDDED SYSTEMS;

EID: 34547165011     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1176254.1176297     Document Type: Conference Paper

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