Efficient 2DMesh Network on Chip (NoC) considering GALS approach

ICCIT 2009 - 4th International Conference on Computer Sciences and Convergence Information Technology

Volumn , Issue , 2009, Pages 841-846

  Rahman, Mohammed Anis Ur ^a   Ahmed, Imtiaj ^b   Rodriguez, Fernando ^a   Islam, Naimul ^c  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

^b UNIVERSITY OF HELSINKI   (Finland)

^c UNIVERSITY OF EAST LONDON   (United Kingdom)

Author keywords

GALS; NoC; RTU; SoC; VHDL

Indexed keywords

COMMUNICATION ARCHITECTURES; COMMUNICATION INFRASTRUCTURE; FEATURE SIZES; HIGH-LEVEL SERVICES; LARGE SYSTEM; MESH NODES; NETWORK INTERFACE; NETWORK ON CHIP; NETWORK-ON-CHIP DESIGN; NEW DESIGN; STANDARD BUS; STATE OF THE ART; SYSTEM ON CHIPS; VLSI SYSTEM;

COMPUTER SCIENCE; DATA TRANSFER; DISTRIBUTED COMPUTER SYSTEMS; INFORMATION TECHNOLOGY; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS;

ROUTERS;

EID: 77749271405     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCIT.2009.303     Document Type: Conference Paper

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