A multi-processor NoC-based architecture for real-time image/video enhancement

Journal of Real-Time Image Processing

Volumn 8, Issue 1, 2013, Pages 111-125

  Saponara, Sergio ^a   Fanucci, Luca ^a   Petri, Esa ^b  

^a UNIVERSITY OF PISA   (Italy)

^b Consorzio Pisa Ricerche scarl ^*  (Italy)

Author keywords

Digital IP cells; Image enhancement; Multi Processor System on Chip (MPSoC); Network on Chip (NoC); Real time image video processing

Indexed keywords

DATA TRANSFER; IMAGE ENHANCEMENT; NETWORK ARCHITECTURE; PACKET SWITCHING; PARALLEL ARCHITECTURES; SERVERS; VIDEO CAMERAS;

65 NM CMOS TECHNOLOGIES; ENHANCEMENT ALGORITHMS; FUNCTIONAL PERFORMANCE; IMPLEMENTATION COMPLEXITY; MULTI PROCESSOR ARCHITECTURE; MULTI PROCESSOR SYSTEM ON CHIPS; NETWORK-ON-CHIP(NOC); REAL-TIME IMAGE/VIDEO PROCESSING;

NETWORK-ON-CHIP;

EID: 84874655473     PISSN: 18618200     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11554-011-0215-8     Document Type: Article

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