Performance and resource optimization of NoC router architecture for master and slave IP cores

CODES+ISSS 2007: International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2007, Pages 155-160

  Leary, Glenn ^a   Mehta, Krishna ^a   Chatha, Karam S ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

FPGA; Network on chip

Indexed keywords

NETWORK-ON-CHIPS; NOC ROUTER ARCHITECTURES; PROCESSOR LOCAL BUS (PLB);

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTERNET PROTOCOLS; MICROPROCESSOR CHIPS; OPTIMIZATION; SOFTWARE ARCHITECTURE;

ROUTERS;

EID: 38849183295     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1289816.1289856     Document Type: Conference Paper

References (12)

1. A. Jalabert, S. Murali, L. Benini, and G. De Mioheli, "XpipesCompiler: A tool for instantiating application specific networks on chip," in Proc. DATE, 2004.
2. A. Andriahantenaina, A. Greiner, Mioro-network for SoC: implementation of a 32-port SPIN network, in: DATE, Munioh, Germany, Maroh 2003.
3. D. Siguenza-Tortosa, J. Nurmi, Proteo: a new approaoh to network-on-chip, in: Proceedings of IASTED International Conference on Communication Systems and Network, Malaga, Spain, 2002.
4. M. Dall'Osso, G. Biooari, L. Giovanninni, D. Bertozzi, L. Benini, Xpipes: a latency insensitive parameterized network-on-chip architecture for multi-processor SoCs, in: Proceedings of ICCD, San Jose, CA, Ootober 2003.
5. M. Millberg, E. Nilsson, R. Thid, S. Kumar, A. Jantsoh, The Nostrum backbone - a communication protocol stack for networks on chip, in: VLSI Design Conference, Mumbai, India, January 2004.
6. J. Dielissen, A. Radulescu, K. Goossens, E. Rijpkema, Concepts and implementation of the Philips network-onchip, in: IP-Based SOC Design, November 2003.
7. E. Bolotin, I. Cidon, R. Ginosar and A. Kolodny, "QNoC: QoS architecture and design process for Network on Chip", Special issue on Networks on Chip, The Journal of Systems Arohiteoture, Deoember 2003.
8. H.-S. Wang, L.-S. Peh, S. Malik, Orion: a power-performanoe simulator for interconnection network, in: International Symposium on Mioroarchitecture, Istanbul, Turkey, November 2002.
9. N. Banerjee, P. Vellanki, K.S. Chatha, A power and performance model for network-on-ohip architectures, in: DATE, 2004.
10. J. Hu, U. Ogras and R. Maroulesou, System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design, IEEE Transactions on CADICS, Vol. 25, No. 12, Deoember 2006.
11. Xilinx Embedded Development Kit, http://www.xilinx.com.
12. http://www.opencores.org