CMOS: Circuit Design, Layout, and Simulation: Third Edition

CMOS: Circuit Design, Layout, and Simulation: Third Edition

Volumn , Issue , 2011, Pages

  Baker, R Jacob ^a  

^a NONE

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EID: 84891562000     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1002/9780470891179     Document Type: Book

References (281)

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32. R. C. Jaeger, Introduction to Microelectronic Fabrication, 2nd ed., volume 5 of the Modular Series on Solid State Devices, Prentice-Hall Publishers, 2002. ISBN 0-20-144494-1
33. S. A. Campbell, The Science and Engineering of Micrelectronic Fabrication, 2nd ed., Oxford University Press, 2001. ISBN 0-19-513605-5
34. J. D. Plummer, M. D. Deal, and P. B. Griffin, Silicon VLSI Technology, Fundamentals, Practice, and Modeling, Prentice-Hall Publishers, 2000. ISBN 978-0130850379
35. R. J. Baker, CMOS: Mixed-Signal Circuit Design, Second Edition, Wiley-IEEE Press, 2009. Covers noise/averaging and the affects on signal-to-noise ratio. Good complement to the material in this chapter.
36. W. T. (Tim) Holman, Private communication, Feb. 2002. Information on how the RMS value of a signal containing l//-noise (and l/f2, l//"3, etc.) grows with measuring time.
37. C. D. Motchenbacher and J. A. Connelly, Low-Noise Electronic System Design, John Wiley and Sons, 1993. ISBN 0-471-57742-1. Excellent reference for low-noise design.
38. R. Sarpeshkar, T. Delbriick, and C. A. Mead, "White Noise in MOS Transistors and Resistors," IEEE Circuits and Devices Magazine, Nov. 1993. Shows that both shot and thermal noise mechanisms in MOSFETs have the same origins.
39. D. M. Binkley, J. M. Rochelle, M. J. Paulus, and M. E. Casey, "A Low-Noise, Wideband, Integrated CMOS Transimpedance Preamplifier for Photodiode Applications," in IEEE Transactions on Nuclear Science, vol. NS-39, no. 4, August 1992, pp. 747-752. Covers the design of low-noise transimpedance amplifiers.
40. H. L. Krauss, C. W. Bostian, and F. H. Raab, Solid State Radio Engineering, John Wiley and Sons, 1980. ISBN 0-471-03018-X. Reference for the design of radio circuits.
41. W. R. Bennett, Electrical Noise, McGraw-Hill, 1960. Fundamental reference on electrical noise. Written by a pioneer in noise theory. No longer in print but available used through various book sellers.
42. A. Van der Ziel, Noise; Sources, Characterization, Measurement, Prentice-Hall. Also written by a pioneer in noise theory.
43. H. F. Friis, "Noise Figures of Radio Receivers," in Proceedings of the IRE (Institute of Radio Engineers), vol. 32, no. 7, 1944, pp. A19-422. Fundamental paper covering noise figure.
44. R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, 4th ed., McGraw-Hill Publishers, 2011. ISBN 978-0-07-338045-2.
45. R. Spencer and M. Ghausi, Introduction to Electronic Circuit Design, Prentice-Hall Publishers, 2003. ISBN 0-201-36183-3.
46. D. J. Comer and D. T. Comer, Fundamentals of Electronic Circuit Design, John Wiley and Sons, 2002. ISBN 0-471-41016-0.
47. D. A. Neamen, Electronic Circuit Analysis and Design, McGraw-Hill Publishers, 2001. ISBN 0-072-45194-7.
48. A. R. Hambley, Electronics, Prentice-Hall Publishers, 2nd ed, 2000. ISBN 0-136-91982-0.
49. M. H. Rashid, Microelectronic Circuits: Analysis and Design, Brookes-Cole Publishing, 1998. ISBN 0-534-95174-0.
50. A. Sedra and K. Smith, Microelectronic Circuits, Oxford University Press, 4th ed., 1998. ISBN 0-195-11663-1.
51. R. T. Howe and C. G. Sodini, Microelectronics: An Integrated Approach, Prentice-Hall Publishers, 1997. ISBN 0-135-88518-3.
52. N. Malik, Electronic Circuits: Analysis, Simulation, and Design, Prentice-Hall Publishers, 1995. ISBN 0-023-74910-5.
53. M. N. Horenstein, Microelectronic Circuits and Devices, Prentice-Hall Publishers, 2nd ed., 1990. ISBN 0-135-83170-9.
54. M. S. Roden, G. L. Carpenter, and C. J. Savant, Electronic Design: Circuits and Systems, Pearson Benjamin Cummings Publishers, 2nd ed, 1990.
55. J. Millman and A. Grabel, Microelectronics, McGraw-Hill Publishers, 2nd ed. 1987. ISBN 0-070-42330-X.
56. F. Bonani and G. Ghione, Noise in Semiconductor Devices: Modeling and Simulation, Springer-Verlag Publishers, 2002. ISBN 3-540-66583-8.
57. C. D. Motchenbacher and J. A. Connelly, Low-Noise Electronic System Design, John Wiley and Sons, 1993. ISBN 0-471-57742-1.
58. H. L. Krauss, C. W. Bostian, and F. H. Raab, Solid State Radio Engineering, John Wiley and Sons, 1980. ISBN 0-471-03018-X.
59. Reimbold, G., "Modified 1/f Trapping Noise Theory and Experiments in MOS Transistors Biased from Weak to Strong Inversion-Influence of Interface States," IEEE Transactions on Electron Devices, vol. ED-31, no. 9, pp. 1190-1198, September, 1984.
60. J. P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley and Sons Publishers, 2002. ISBN 0-471-12704-3.
61. R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI-Design Techniques for Analog and Digital Circuits, McGraw-Hill Publishing Company, 1990. ISBN 0-07-023253-9.
62. K. Bernstein, K. M. Carrig, C. M. Durham, P. R. Hansen, D. Hogenmiller, E. J. Nowak, and N. J. Rohrer, High Speed CMOS Design Styles, Springer, 1999. ISBN 978-0792382201.
63. J. P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley and Sons Publishers, 2002. ISBN 0-471-12704-3.
64. M. I. Elmasry, Digital MOS Integrated Circuits II, IEEE Press, 1992. ISBN 0-87942-275-0, IEEE order number: PC0269-1.
65. R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI-Design Techniques for Analog and Digital Circuits, McGraw-Hill Publishing Co., 1990. ISBN 0-07-023253-9.
66. I. Sutherland, R. F. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann, 1999. ISBN 978-1558605572
67. M. I. Elmasry, Digital MOS Integrated Circuits II, IEEE Press, 1992. ISBN 0-87942-275-0, IEEE order number: PC0269-1.
68. J. P. Uyemura, Circuit Design for Digital CMOS VLSI, Kluwer Academic Publishers, 1992.
69. M. Shoji, CMOS Digital Circuit Technology, Prentice-Hall, 1988. ISBN 0-13-138850-9.
70. M. I. Elmasry, Digital MOS Integrated Circuits II, IEEE Press, 1992. ISBN 0-87942-275-0, IEEE order number: PC0269-1.
71. J. P. Uyemura, Circuit Design for Digital CMOS VLSI, Kluwer Academic Publishers, 1992.
72. M. Shoji, CMOS Digital Circuit Technology, Prentice-Hall, 1988. ISBN 0-13-138850-9.
73. K. Bernstein, K. M. Carrig, C. M. Durham, P. R. Hansen, D. Hogenmiller, E. J. Nowak, and N. J. Rohrer, High Speed CMOS Design Styles, Springer, 1999. ISBN 978-0792382201.
74. J. Yuen and C. Svensson, "New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings," IEEE Journal ofSolid-State Circuits, vol. 32, no. 1, pp. 62-69, 1997.
75. M. I. Elmasry, Digital MOS Integrated Circuits II, IEEE Press, 1992. ISBN 0-87942-275-0, IEEE order number: PC0269-1.
76. J. P. Uyemura, Circuit Design for Digital CMOS VLSI, Kluwer Academic Publishers, 1992.
77. R. L. Geiger, P. E. Allen, and N. R. Strader, VLSI-Design Techniques for Analog and Digital Circuits, McGraw-Hill Publishing Co., 1990. ISBN 0-07-023253-9.
78. N. H. E. Weste and D. Harris, Principles of CMOS VLSI Design, 4th ed., Addison-Wesley, 2010. ISBN 978-0321547743.
79. J. P. Uyemura, Introduction to VLSI Circuits and Systems, John Wiley and Sons Publishers, 2002. ISBN 0-471-12704-3.
80. C. Saint and J. Saint, IC Mask Design: Essential Layout Techniques, McGraw-Hill, 2002. ISBN 0-071-38996-2. Companion book for reference [4].
81. C. Saint and J. Saint, IC Layout Basics: A Practical Guide, McGraw-Hill, 2001. ISBN 0-071-38625-4. Very good introductory book on IC Layout.
82. D. Clein, CMOS IC Layout: Concepts, Methodologies, and Tools, Newnes Publishers, 2000. ISBN 0-750-67194-7. Excellent introductory book for CMOS IC layout. Covers the entire layout process.
83. J. Uyemura, Physical Design of CMOS Integrated Circuits Using L-EDIT, PWS Publishing Co., 1995. ISBN 0-534-94326-8. Covers the use of the L-EDIT layout software.
84. Kerth, Donald A. "Floorplanning-Lecture Notes," Crystal Semiconductor, Inc.
85. Kerth, Donald A. "Analog Tricks of the Trade-Lecture Notes." Crystal Semiconductor, Inc.
86. D. V. Heinbuch, CMOS3 Cell Library, Addison-Wesley, 1988. ISBN 0-201-11257-4. Excellent source of layout examples.
87. B. Keeth, R. J. Baker, B. Johnson, and F. Lin, DRAM Circuit Design: Fundamental and High-Speed Topics, Second Edition, Wiley-IEEE, 2008. ISBN 978-0-470-18475-2
88. B. Jacob, S. W. Ng, and D. T. Wang, Memory Systems: Cache, DRAM, Disk, Morgan Kaufmann, 2008. ISBN 978-0123797513
89. J. E. Brewer and M. Gill, Nonvolatile Memory Technologies with Emphasis on Flash: A Comprehensive Guide to Understanding and Using Flash Memory Devices, Wiley-IEEE, 2008. ISBN 978-0471770022
90. K. Itoh, VLSI Memory Chip Design, Springer-Verlag Publishers, 2001. ISBN 3-5406-7820-4
91. W. D. Brown and J. E. Brewer (eds.), Nonvolatile Semiconductor Memory Technology: A Comprehensive Guide to Understanding and Using NVSM Devices, John Wiley and Sons Publishers, 1998. ISBN 0-7803-1173-6
92. A. K. Sharma, Semiconductor Memories: Technology, Testing and Reliability, John Wiley and Sons Publishers, 1997. ISBN 0-7803-1000-4
93. T. Mohihara, et al., "Disk-Shaped Capacitor Cell for 256Mb Dynamic Random-Acess Memory," Japan Journal of Applied Physics, vol. 33, part 1, no. 8, pp. 4570-4575, August 1994.
94. K. Sagara, et al., "Recessed Memory Array Technology for a Double Cylindrical Stacked Capacitor Cell of 256M DRAM," IEICE Trans. Electron., vol. E75-C, No. 11, pp. 1313-1322, November 1992.
95. T. Hamada, "A Split-Level Diagonal Bit-Line (SLDB) Stacked Capacitor Cell for 256Mb DRAMs," 1992 IEDM Technical Digest, pp. 799-802.
96. J. H. Ahn et al., "Micro Villus Patterning (MVP) Technology for 256Mb DRAM Stack Cell," 1992 Symposium on VLSI Technical Digest of Technical Papers, pp. 12-13.
97. M. I. Elmasr, Digital MOS Integrated Circuits II, IEEE Press, 1992. ISBN 0-87942-275-0
98. B. Prince, Semiconductor Memories: A Handbook of Design Manufactur, and Application, 2nd ed., John Wiley and Sons Publishers, 1991. ISBN 0-471-92465-2
99. R. D. Pashley and S. K. Lai, "Flash Memories: The Best of Two Worlds," IEEE Spectrum, 1989, pp. 30-33.
100. D. Frohman-Bentchkowsky, "FAMOS-A New Semiconductor Charge Storage Device," Solid-State Electronics, vol. 17, pp. 517-529, 1974.
101. E. H. Snow, "Fowler-Nordheim Tunneling in Si02 Films," Solid-State Communications, vol. 5, pp. 813-815, 1967. Additional Readings Covering Analog Applications of Floating Gate Devices
102. C. T. Charles and R. R. Harrison, "A Floating Gate Common Mode Feedback Circuit for Low Noise Amplifiers," Proceedings of the Southwest Symposium on Mixed-Signal Design, Las Vegas, NV, pp. 180-185, February 23-25, 2003.
103. F. Adil, G. Serrano, and P. Hasler, "Offset Removal Using Floating-Gate Circuits for Mixed-Signal Systems," Proceedings of the Southwest Symposium on Mixed-Signal Design, Las Vegas, NV, pp. 190-195, February 23-25, 2003.
104. R. R. Harrison, J. A. Bragg, P. Hasler, B. A. Minch, and S. P. Deweerth, "A CMOS programmable analog memory-cell array using floating-gate circuits," IEEE Transactions on Circuits and Systems-II, vol. 48, no. 1, pp. 4-11, 2001.
105. F. Munoz, A. Torralba, R. G. Carvajal, J. Tombs, and J. Ramirez Angulo, "Floating-Gate based tunable CMOS low-voltage linear transconductor and its application to HF gm-C filter design," IEEE Transactions on Circuits and Systems, vol. 48, no. 1, January 2001, pp. 106-110.
106. E. Sänchez-Sinencio and A. G. Andreou, "Low-Voltage/Low-Power Integrated Circuits and Systems: Low-Voltage Mixed-Signal Circuits," IEEE Press, 1999. ISBN 0-7803-3446-9
107. P. M. Furth and H. A. Ommani, "A 500-nW floating-gate amplifier with programmable gain," 41st Midwest Symp. Circuits and Systems, South Bend, IN, August 1998.
108. J. Ramirez-Angulo, "Ultracompact Low-voltage Analog CMOS Multiplier Using Multiple Input Floating Gate Transistors," 1996 European Solid State Circuits Conference, pp. 99-103.
109. J. Ramirez-Angulo, S.C. Choi, and G. Gonzalez-Altamirano, "Low-Voltage OTA Architectures Using Multiple Input Floating gate Transistors," IEEE Transactions on Circuits and Systems, vol. 42, no. 12, pp. 971-974, November 1995.
110. C. G. Yu and R. L. Geiger, "Very Low Voltage Operational Amplifiers Using Floating Gate MOS Transistors," IEEE Symp. Circuits Sys., vol. 2, pp. 1152-1155,1993.
111. L. R. Carley, "Trimming Analog Circuits Using Floating-Gate Analog MOS Memory," IEEE Journal of Solid-State Circuits, vol. SC-24, pp. 1569-1575, 1989.
112. J. Sweeney and R. L. Geiger, "Very High Precision Analog Trimming Using Floating Gate MOSFETs," Proceedings of the European Converence on Circuit Theory and Design, Brighton, United Kingdom, September 1989, pp. 652-655.
113. R. J. Baker, CMOS: Mixed-Signal Circuit Design, Second Edition, Wiley-IEEE Press, 2009.
114. R. J. Baker, "Method and system for reducing mismatch between reference and intensity paths in analog to digital converters in CMOS active pixel sensors," US Patent 7,515,188, April 7, 2009.
115. J. Taylor and R. J. Baker, "Method and apparatus for sensing flash memory using delta-sigma modulation," US Patent 7,366,021, April 29,2008.
116. R. J. Baker, "Per column one-bit ADC for image sensors," US Patent 7,456,885, November 25, 2008.
117. R. J. Baker, "Resistive memory element sensing using averaging," US Patent 6,504,750, January 7, 2003.
118. R. J. Baker, "Input and output buffers having symmetrical operating characteristics and immunity from voltage variations," US Patent 7,102,932, September 5, 2006.
119. F. Pan and T. Samaddar, Charge Pump Circuit Design, McGraw-Hill, 2006. ISBN 978-0071470452.
120. H. Lin, N.-H. Chen, and J. Lu, "Design of Modified Four-Phase CMOS Charge Pumps for Low-Voltage Flash Memories," Journal of Circuits, Systems, and Computers, Vol. 11, No. 4, pp. 393-403, 2002. Excellent paper.
121. N. Otsuka and M. A. Horowitz, "Circuit techniques for 1.5-V power supply flash memory," IEEE Journal of Solid-State Circuits, Vol. 32, pp. 1217-1230, August 1997.
122. M. Bazes, "Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers," IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, pp. 165-168, February 1991.
123. J. F. Dickson, "On-Chip High-Voltage Generation in MNOS (sic) Integrated Circuits Using an Improved Voltage Multiplier Technique," IEEE Journal of Solid State Circuits, Vol. SC-11, No. 3, June 1976.
124. J. Millman and H. Taub, Pulse, Digital, and Switching Waveforms, McGraw-Hill Publishers, 1965. ISBN 07-042386-5. Information on multivibrators and oscillators.
125. O. H. Schmitt, "A Thermionic Trigger," Journal of Scientific Instruments, Vol. XV, pp. 24-26, No. 1, Jan. 1938. Information on the "Schmitt trigger."
126. R. E. Best, Phase-Locked Loops: Desig, Simulation, and Applications, McGraw-Hill, 6th ed., 2007. ISBN 978-0071493758. Excellent book covering PLL design.
127. W. F. Egan, Phase-Lock Basics, John Wiley and Sons, 1998. ISBN 0-4712-4261-6 Good introduction to PLLs. See also the same author's Frequency Synthesis by Phase Lock.
128. B. Razavi, Monolithic Phase-Locked-Loops and Clock Recovery Circuits, IEEE Press, 1996. ISBN 0-7803-1149-3. Good tutorial and collection of papers.
129. J. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques", IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732, 1996. Excellent paper discussing the design of PLLs and DLLs using self-biased techniques for very wideband operation.
130. D. H. Wolaver, Phase-Locked Loop Circuit Design, Prentice-Hall, 1991. ISBN 0-1366-2743-9. Another excellent book covering PLL design.
131. S. Haykin, An Introduction to Analog and Digital Communications, John Wiley and Sons, 1989. ISBN 0-471-85978-8. Covers distortionless transmission.
132. M. G. Johnson and E. L. Hudson, "A Variable Delay Line PLL for CPU-Coprocessor Synchronization," IEEE Journal of Solid-State Circuits, vol. SC-23, pp. 1218-1223, October, 1988. Classic paper presenting the concept of a delay-locked loop.
133. C. R. Hogge, Jr., "A Self Correcting Clock Recovery Circuit," IEEE Journal of Lightwave Technology, vol. LT-3, pp. 1312-1314, December 1985. Paper presenting the "Hogge" phase detector.
134. F. M. Gardner, "Charge-Pump Phase-Lock Loops," IEEE Transactions on Communications, COM-28, no. 11, pp. 1849-1858, November 1980. The paper first discussing charge pump PLLs.
135. S. J. Lovett, M. Welten, A. Mathewson, and B. Mason, "Optimizing MOS transistor mismatch," IEEE Journal of Solid-State Circuits, vol. 33, pp. 147-150, January 1998.
136. K. de Langen and J. H. Huijsing, "Compact low-voltage power-efficient operational amplifier cells for VLSI," IEEE Journal of Solid-State Circuits, vol. 33, pp. 1482-1496, October 1998.
137. P. Larsson, "Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance," IEEE Journal of Solid-State Circuits, vol. 32, pp. 574-576, April 1997.
138. C. Yu and R. L. Geiger, "An automatic offset compensation scheme with ping-pong control for CMOS operational amplifiers," IEEE Journal of Solid-State Circuits, vol. 29, pp. 601-610, May 1994.
139. R. G. Eschauzier, R. Hogervorst, and J. H. Huijsing, "A programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested Miller compensation for 120 dB gain and 6 MHz UGF," IEEE Journal of Solid-State Circuits, vol. 29, pp. 1497-1504, December 1994.
140. R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. H. Huijsing, "A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries," IEEE Journal of Solid State Circuits, vol. 29, pp. 1505-1513, December 1994.
141. E. Säckinger and W. Guggenbühl, "A High-Swing, High-Impedance MOS Cascode Circuit," IEEE Journal of Solid-State Circuits, vol. 25, pp. 289-298, February 1990.
142. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433-1439, October 1989.
143. K. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, "Characterisation and Modeling of Mismatch in MOS Transistors for Precision Analog Design," IEEE Journal of Solid-State Circuits, vol. 21, pp. 1057-1066, December 1986.
144. J. Shyu, F. Krummenacher, and G. C. Temes, "Random error effects in matched MOS capacitors and current sources," IEEE Journal of Solid-State Circuits, vol. 19, pp. 948-956, December 1984.
145. P. R. Gray and R. G. Meyer, "MOS operational amplifier design-A tutorial overview," IEEE Journal of Solid-State Circuits, vol. 17, pp. 969-982, December 1982.
146. J. L. McCreary, "Matching properties, and voltage and temperature dependence of MOS capacitors," IEEE Journal of Solid-State Circuits, vol. 16, pp. 608-616, December 1981.
147. W. Steinhagen and W. L. Engl, "Design of integrated analog CMOS circuits-A multichannel telemetry transmitter," IEEE Journal of Solid-State Circuits, vol. 13, pp. 799-805, December 1978.
148. E. Vittoz and J. Fellrath, "CMOS analog integrated circuits based on weak inversion operations," IEEE Journal of Solid-State Circuits, vol. 12, pp. 224-231, June 1977.
149. K. N. Leung, P. K. T. Mok, W. Ki, and J. K. O. Sin, "Three-stage large capacitive load amplifier with damping-factor-control frequency compensation," IEEE Journal of Solid-State Circuits, vol. 35, pp. 221-230, February 2000.
150. A. B. Dowlatabadi, "A robust, load-insensitive pad driver," IEEE Journal of Solid-State Circuits, vol. 35, pp. 660-665, April 2000.
151. B. Razavi, "CMOS technology characterization for analog and RF design," IEEE Journal of Solid-State Circuits, vol. 34, pp. 268-276, March 1999.
152. K. de Langen and J. H. Huijsing, "Compact low-voltage power-efficient operational amplifier cells for VLSI," IEEE Journal of Solid-State Circuits, vol. 33, pp. 1482-1496, October 1998.
153. P. E. Allen, B. J. Blalock, and G. A. Rincon, "A IV CMOS Opamp using Bulk-Driven MOSFETs," IEEE International Solid-State Circuits Conference, vol. 38, pp. 192-193, February 1995.
154. R. G. Eschauzier, R. Hogervorst, and J. H. Huijsing, "A programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested Miller compensation for 120 dB gain and 6 MHz UGF," IEEE Journal of Solid-State Circuits, vol. 29, pp. 1497-1504, December 1994.
155. R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. H. Huijsing, "A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries," IEEE Journal of Solid State Circuits, vol. 29, pp. 1505-1513, December 1994.
156. A. A. Abidi, "On the operation of cascode gain stages," IEEE Journal of Solid-State Circuits, vol. 23, pp. 1434-1437, December 1988.
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