A 14-b 20-MSamples/s CMOS pipelined ADC

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 6, 2001, Pages 997-1001

  Chen, Hsin Shu ^a,b   Song, Bang Sup ^a,c   Bacrania, Kantilal ^a,b  

^a IEEE   (United States)

^b INTERSIL CORPORATION   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Analog to digital converter; Capacitor error averaging; CMOS pipeline

Indexed keywords

CAPACITOR ERROR AVERAGING; CMOS PIPELINE; DIFFERENTIAL NONLINEARITY; SPURIOUS FREE DYNAMIC RANGE;

CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; DIGITAL FILTERS; FAST FOURIER TRANSFORMS; OPERATIONAL AMPLIFIERS; SIGNAL FILTERING AND PREDICTION; SIGNAL TO NOISE RATIO; THERMAL NOISE;

ANALOG TO DIGITAL CONVERSION;

EID: 0035368887     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.924862     Document Type: Article

References (13)

1. A 12-bit 1-MSample/s capacitor error-averaging pipelined A/D converter
2. A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter
3. A 12-bit 1-MHz two-step flash ADC
4. A mismatch independent DNL-pipelined analog to digital converter
5. A 13-b 10-MSample/s ADC digitally calibrated with oversampling delta-sigma converter
6. A 15-b 5-MSample/s low-spurious CMOS ADC
7. A 13-b 40-MSample/s CMOS pipelined folding ADC with background offset trimming
8. A 14-b 100-MSample/s 3-stage A/D converter
9. A nyquist-rate pipelined oversampling A/D converter
10. A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter
11. A 240-Mb/s 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter