메뉴 건너뛰기




Volumn 42, Issue 11, 1995, Pages 971-974

Low-Voltage Circuits Building Blocks Using Multiple-Input Floating-Gate Transistors

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; ELECTRIC PROPERTIES; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; WAVEFORM ANALYSIS;

EID: 0029404244     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.477210     Document Type: Article
Times cited : (145)

References (8)
  • 1
    • 27944492851 scopus 로고
    • A functional MOS transistor featuring gate-level weighted sum and threshold operations
    • June
    • T. Shibata and T. Ohmi, “A functional MOS transistor featuring gate-level weighted sum and threshold operations,” IEEE Trans. Electron Devices, vol. 39, pp. 1444–1455, June 1992.
    • (1992) IEEE Trans. Electron Devices , vol.39 , pp. 1444-1455
    • Shibata, T.1    Ohmi, T.2
  • 2
    • 0343208347 scopus 로고
    • Multiple input floating gate MOS differential amplifiers and applications of analog computation
    • May, San Diego, CA
    • K. Yang and A. G. Andreou, “Multiple input floating gate MOS differential amplifiers and applications of analog computation,” in Proc. ISCAS 1992, San Diego, CA, May 10–13, 1992, pp. 1212–1216.
    • (1992) Proc. ISCAS , pp. 1212-1216
    • Yang, K.1    Andreou, A.G.2
  • 3
    • 0026172110 scopus 로고
    • Analog floating gate-synapses for general purpose VLSI neural computation
    • June
    • B. W. Lee, B. J. Sheu, and H. Yang, “Analog floating gate-synapses for general purpose VLSI neural computation,” IEEE Trans. Circuits Syst., vol. 38, pp. 654–657, June 1991.
    • (1991) IEEE Trans. Circuits Syst. , vol.38 , pp. 654-657
    • Lee, B.W.1    Sheu, B.J.2    Yang, H.3
  • 4
    • 0026121022 scopus 로고
    • A floating gate MOSFET with tunneling injector fabricated using a standard double polysilicon CMOS process
    • Mar.
    • A. Thomsen and M. Brooke, “A floating gate MOSFET with tunneling injector fabricated using a standard double polysilicon CMOS process,” IEEE Electron Device Lett., vol. 12, pp. 111–113, Mar. 1991.
    • (1991) IEEE Electron Device Lett. , vol.12 , pp. 111-113
    • Thomsen, A.1    Brooke, M.2
  • 5
    • 0028573623 scopus 로고
    • Floating gate charge sharing: A novel circuit for analog trimming
    • London, UK, May 30/June 2
    • W. Gao and M. Snelgrove, “Floating gate charge sharing: A novel circuit for analog trimming,” in Proc. ISCAS 1994, London, UK, May 30/June 2, 1994, pp. 315–318.
    • (1994) Proc. ISCAS 1994 , pp. 315-318
    • Gao, W.1    Snelgrove, M.2
  • 6
    • 0028370929 scopus 로고
    • A novel aproach to controlled programming of tunnel-based floating gate MOSFETs
    • Feb.
    • M. Lanzoni, L. Briozzo, and B. Ricco, “A novel aproach to controlled programming of tunnel-based floating gate MOSFETs,” IEEE J. Solid State Circuits, vol. 29, pp. 147–150, Feb. 1994.
    • (1994) IEEE J. Solid State Circuits , vol.29 , pp. 147-150
    • Lanzoni, M.1    Briozzo, L.2    Ricco, B.3
  • 7
    • 0024122968 scopus 로고
    • An analog trimming circuit based on a floating gate
    • Dec.
    • E. Sackmger and W. Guggenbuhl, “An analog trimming circuit based on a floating gate,” IEEE J. Solid State Circuits, vol. 23, pp. 1437—1440, Dec. 1988.
    • (1988) IEEE J. Solid State Circuits , vol.23 , pp. 1437
    • Sackmger, E.1    Guggenbuhl, W.2
  • 8


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.