A Variable Delay Line PLL for CPU-Coprocessor Synchronization

IEEE Journal of Solid-State Circuits

Volumn 23, Issue 5, 1988, Pages 1218-1223

  Johnson, Mark G ^a   Hudson, Edwin L ^a  

^a MIPS Technologies Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS, DIGITAL -- SYNCHRONIZATION; ELECTRONIC CIRCUITS, DELAY TYPE; INTEGRATED CIRCUITS;

CMOS INTEGRATED CIRCUITS; CPU-COPROCESSOR SYNCHRONIZATION; FLOATING POINT COPROCESSORS; FULLY INTEGRATED PHASE LOCKED LOOPS; VARIABLE DELAY LINE;

PHASE LOCKED LOOPS;

EID: 0024091885     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.5947     Document Type: Article

References (6)

1. J. Moussouris et al, “A CMOS RISC processor with integrated system functions.” in Proc. 1986 COMPCON. IEEE, pp. 126–131.
2. D-K. Jeong, G. Borriello, D. Hodges, and R. Katz. “Design of PLL-based clock generation circuits,” IEEE J. Solidstate Circuits. vol. SC-22, no. 2, pp. 255–261, Apr. 1987.
3. M. Bazes, “A novel precision MOS synchronous delay line,” IEEE J. Solidstate Circuits, vol. SC-20, no. 6, pp. 1265–1271, Dec. 1985.
4. M. Forsyth, W. Jaffe, D. Tanksalvala, J. Wheeler, and J. Yetter, “A 32-bit VLSI CPU with 15-MIPS peak performance,” IEEE J. Solidstate Circuits, vol. SC-22, no. 5, pp. 768–775, Oct. 1987.
5. F. Gardner, “Charge-pump phaselock loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849–1858, Nov. 1980.
6. M. Johnson and E. Hudson. “A variable delay line phase locked loop for CPU-coprocessor synchronization,” in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 142–143.