Microprocessor design using 3D integration technology

Three Dimensional System Integration: IC Stacking Process and Design

Volumn , Issue , 2011, Pages 211-236

  Xie, Yuan ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84889863261     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-1-4419-0962-6_9     Document Type: Chapter

References (40)

1. Bernstein K (2006) Introduction to 3D integration. In: Tutorials in international solid state circuits conference (ISSCC)
2. Black B, Annavaram M, Brekelbaum N, DeVale J, Jiang L, Loh GH, McCauley D, Morrow P, Nelson DW, Pantuso D, Reed P, Rupley J, Shankar S, Shen J, Webb C (2006) Die stacking 3D microarchitecture. In: MICRO, pp 469-479
3. Borkar S (2008) 3D Technology: A System Perspective. In: Technical digest of the international 3D system integration conference
4. Carloni L, Pande P, Xie Y (2009) Networks-on-chip in emerging intercoonect paradigms: Advantages and challenges. In: International symposium on networks-on-chips, pp 93-102
5. Chen KN, Fan A, Tan CS, Reif R (2004) Contact resistance measurement of bonded copper interconnects for three-dimensional integration technology. IEEE Electron Device Lett, 25(1):10-12
6. Davis WR, Wilson J, Mick S, Xu J, Hua H, Mineo C, Sule AM, Steer M, Franzon PD (2005) Demystifying 3D ICs: The pros and cons of going vertical. IEEE Des Test Comput, 22(6):498-510
7. Dong X, Wu X, Sun G, Xie Y, Li H, Chen Y (2008) Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement. In: DAC '08: Proceedings of the 45th annual design automation conference, pp 554-559, ACM, New York, NY, USA
8. Dongkook P, Eachempati S, Das R, Mishra AK, Xie Y, Vijaykrishnan N, Das CR (2008) MIRA: A multi-layered on-chip interconnect router architecture. In: International symposium on computer architecture (ISCA), pp 251-261
9. Egawa R, Tada J, Kobayashi H, Goto G (2009) Evaluation of fine grain 3D integrated arithmetic units. In: IEEE International 3D system integration conference, pp 1-8
10. Garrou P (2008) Introduction to 3D integration. In: Handbook of 3D integration: technology and applications using 3D integrated circuits, Wiley, London
11. Jacob P, Zia A, Chu M, Kim JW, Kraft R, McDonald JF, Bernstein K(2008) Mitigating memory wall effects in high clock rate and multi-core CMOS 3D ICs: Processor memory stacks. Proceedings of IEEE, 96(10)
12. Joyner J, Zarkesh-Ha P, Meindl J (2001) A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC). In: Proceedings of the 14th annual IEEE international ASIC/SOC conference, pp 147-151
13. Kang YH, Jung SM, Jang JH, Moon JH, Cho WS, Yeo CD, Kwak KH, Choi BH, Hwang BJ, Jung WR, Kim SJ, Kim JH, Na JH, Lim H, Jeong JH, Kim K (2004) Fabrication and characteristics of novel load PMOS SSTFT (stacked single-crystal thin film transistor) for 3-dimen-tional SRAM memory cell. In: Proceedings of IEEE international SOI conference, pp 127-129
14. Kgil T, D'Souza S, Saidi A, Binkert N, Dreslinski R, Mudge T, Reinhardt S, Flautner K (2006) PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor. In: ASPLOS, pp 117-128
15. Kim J, Nicopoulos C, Park D, Das R, Xie Y, Vijaykrishnan N, Das C (2007) A novel dimen-sionally-decomposed router for on-chip communication in 3D architectures. In: Proceedings of the annual international symposium on computer architecture ACM SIGARCH Comput Archit News, 35(2):138-149
16. Lee KW, Nakamura T, Ono T, Yamada Y, Mizukusa T, Hashimoto H, Park KT, Kurino H, Koyanagi M (2000) Three-dimensional shared memory fabricated using wafer stacking technology. In: Technical digest of the international electron devices meeting, pp 228-229
17. Li F, Nicopoulos C, Richardson T, Xie Y, Vijaykrishnan N, Kandemir M (2006) Design and management of 3D chip multiprocessors using network-in-memory. In: International symposium on computer architecture (ISCA'06) ACM SIGARCH Comput Archit News, 34(2):130-141
18. Loh GH (2008) 3D-stacked memory architectures for multi-core processors. In: International symposium on computer architecture (ISCA), pp 453-464
19. Loh GH (2009) Extending the effectiveness of 3D-stacked dram caches with an adaptive multi-queue policy. In: International symposium on microarchitecture (MICRO), pp 201-212
20. Loh GH, Xie Y, Black B (2007) Processor design in 3D die-stacking technologies. IEEE Micro, 27(3):31-48
21. Mayega J, Erdogan O, Belemjian PM, Zhou K, McDonald JF, Kraft RP (2003) 3D direct vertical interconnect microprocessors test vehicle. In: Proceedings of the 13th ACM great lakes symposium on VLSI (GLSVLSI), pp 141-146
22. Ouyang J, Sun G, Chen Y, Duan L, Zhang T, Xie Y, Irwin M (2009) Arithmetic unit design using 180nm TSV-based 3D stacking technology. IEEE International 3D system integration conference, pp 1-4
23. Palacharla S, Jouppi NP, Smith JE (1997) Complexity-effective superscalar processors. ACM SIGARCH Comput Archit News, 25(2):206-218
24. Puttaswamy K, Loh GH (2005) Implementing caches in a 3D technology for high performance processors. In: ICCD '05: Proceedings of the 2005 international conference on computer design, pp 525-532, IEEE Computer Society, Washington, DC, USA
25. Puttaswamy K, Loh GH (2007) Scalability of 3D-integrated arithmetic units in high-performance microprocessors. In: Design automation conference, pp 622-625
26. Stackhouse B, Bhimji S, Bostak C, Bradley D, Cherkauer B, Desai J, Francom E, Gowan M, Gronowski P, Krueger D, Morganti C, Troyer S (2009) A 65nm 2-billion transistor quad-core itanium processor. IEEE J Solid-State Circuits, 44(1):18-31
27. Sun G, Dong X, Xie Y, Li J, Chen Y (2009) A novel 3D stacked MRAM cache architecture for CMPs. In: International symposium on high performance computer architecture, pp 239-249
28. Tremblay M, Chaudhry S (2008) A third-generation 65nm 16-core 32-thread plus 32-scout-thread CMT SPARC processor. In: IEEE International solid-state circuits conference, pp 82-83
29. Tsai Y-F, Wang F, Xie Y, Vijaykrishnan N, Irwin MJ (2008) Design space exploration for threedimensional cache. IEEE TVLSI, 16(4):444-455
30. Tsai Y-F, Xie Y, Narayanan V, Irwin MJ (2005) Three-dimensional cache design exploration using 3DCacti. In: IEEE International conference on computer design, pp 519-524
31. Vaidyanathan B, Hung W-L, Wang F, Xie Y, Narayanan V, Irwin MJ (2007) Architecting microprocessor components in 3D design space. In: VLSI design, pp 103-108
32. Vangal S, Howard J, Ruhl G, Dighe S, Wilson H, Tschanz J, Finan D, Iyer P, Singh A, Jacob T, Jain S, Venkataraman S, Hoskote Y, Borkar N (2007) An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS. pp 98-589
33. Vangal SR, Howard J, Ruhl G, Dighe S, Wilson H, Tschanz J, Finan D, Singh A, Jacob T, Jain S, Erraguntla V, Roberts C, Hoskote Y, Borkar N, Borkar S (2008) An 80-tile Sub-100-W TeraFLOPS processor in 65-nm CMOS. IEEE J Solid-State Circuits, 43(1):29-41
34. Vantrease D, Schreiber R, Monchiero M, McLaren M, Jouppi NP, Fiorentino M, Davis A, Binkert N, Beausoleil RG, Ahn JH (2008) Corona: System implications of emerging nanopho-tonic technology. In: Proceedings of the 35th international symposium on computer architecture, pp 153-164
35. Wu X, Li J, Zhang L, Speight E, Xie Y (2009) Hybrid cache architecture. In: International symposium on computer architecture (ISCA)
36. Xie Y, Cong J, Sapatnekar S (2009) Three-dimensional integrated circuit design: EDA, design and microarchitectures. Springer, New York
37. Xie Y, Loh G, Black B, Bernstein K (2006) Design space exploration for 3D architectures. ACM J Emerg Technol Comput Syst, 2(2):65-103
38. Xu Y, Du Y, Zhao B, Zhou X, Zhang Y, Yang J(2009) A low-radix and low-diameter 3D interconnection network design. In: International symposium on high performance computer architecture, pp 30-42
39. Zhang K, Bhattacharya U, Chen Z, Hamzaoglu F, Murray D, Vallepalli N, Wang BZY, Bohr M (2004) A SRAM design on 65nm CMOS technology with integrated leakage reduction scheme. In: VLSI technology digest of technical papers, pp 294-295
40. Dong X, Xie Y (2009) System-level cost analysis and design exploration for 3D ICs. In: Asia and South Pacific design automation conference, pp 234-241