A 65 nm 2-billion transistor quad-core itanium processor

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 1, 2009, Pages 18-31

  Stackhouse, Blaine ^a   Bhimji, Sal ^a   Bostak, Chris ^a   Bradley, Dave ^a   Cherkauer, Brian ^a   Desai, Jayen ^a   Francom, Erin ^a   Gowan, Mike ^a   Gronowski, Paul ^a   Krueger, Dan ^a   Morganti, Charles ^a   Troyer, Steve ^a  

^a INTEL CORPORATION   (United States)

Author keywords

65 nm process technology; Circuit design; Clock distribution; Computer architecture; Microprocessor; On die cache; Voltage domains

Indexed keywords

65-NM PROCESS TECHNOLOGY; CIRCUIT DESIGN; CLOCK DISTRIBUTION; MICROPROCESSOR; ON-DIE CACHE; VOLTAGE DOMAINS;

COMPUTERS; COPPER; DIES; ELECTRIC CLOCKS; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; OPTICAL INTERCONNECTS; TELECOMMUNICATION SYSTEMS; TRANSISTORS;

COMPUTER ARCHITECTURE;

EID: 58149218299     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2007150     Document Type: Conference Paper

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