Arithmetic unit design using 180nm TSV-based 3D stacking technology

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Ouyang, J ^a   Sun, G ^a   Chen, Y ^a   Duan, L ^a   Zhang, T ^a   Xie, Y ^a   Irwin, M J ^a  

^a The Center for Nanotechnology Education and Utilization   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D STACKING TECHNOLOGY; 3D TECHNOLOGY; ARITHMETIC UNIT; LINCOLN LABORATORY; PLACE AND ROUTE; PROTOTYPE CHIP; THROUGH-SILICON-VIA;

FREQUENCY MULTIPLYING CIRCUITS; PROGRAM PROCESSORS;

THREE DIMENSIONAL;

EID: 70549092211     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306565     Document Type: Conference Paper

References (11)

1. M.M. Ziegler and M.R. Stan, A unified design space for regular parallel prefix adders, Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, Vol.2, pp.1386-1387, 2004.
2. Z. Huang and M.D. Ercegovac, Effect of wire delay on the design of prefix adders in deep-submicron technology, Signals, Systems and Computers, Asilomar Conference on, Vol.2, pp.1713-1717, 2000.
3. F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, and M. Kandemir, Design and management of 3D chip multiprocessors using network-in-memory, Computer Architecture, International Symposium on, pp. 130-141, 2006.
4. Y.-F. Tsai, F. Wang, Y. Xie, N. Vijaykrishnan, and M.J. Irwin. Design space exploration for 3-D cache. Very Large Scale Integration Systems, IEEE Transactions on, Iss.16, Vol.4, pp.444-455, 2008.
5. K. Puttaswamy and G.H. Loh, Implementing register files for highperformance microprocessors in a die-stacked (3D) technology, Emerging VLSI Technologies and Architectures, IEEE Computer Society Annual Symposium on, 2006.
6. B. Vaidyanathan, W.-L. Hung, F. Wang, Y. Xie, V. Narayanan, and M.J. Irwin, Architecting microprocessor components in 3D design space, VLSI Design, International Conference on, pp.103-108, 2007.
7. K. Puttaswamy and G.H. Loh, Scalability of 3d-integrated arithmetic units in high-performance microprocessors, Design Automation Conference, pp.622-625, 2007.
8. P.M. Kogge and H.S. Stone, A parallel algorithm for the efficient solution of a general class of recurrence equations, Computers, IEEE Transactions on, Vol.22, pp.786-793, 1973.
9. K.F. Pang, H.-W. Soong, R. Sexton, and P.-H. Ang, Generation of high speed CMOS multiplier-accumulators, Electronic Devices Meeting, 1963 Internationl, pp.217-220, 1988.
10. MIT Lincoln Lab, MITLL Low Power FDSOI CMOS Process Design Guide, 6th Edition, 2008.
11. H. Hao, Design and verification methodology for complex three-dimensional digital integrated circuit, PhD thesis, North Carolina State University, 2006.