Introduction to 3D Integration

Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits

Volumn 1, Issue , 2008, Pages 1-11

  Garrou, Philip ^a  

^a Microelectronic Consultants of North Carolina   (United States)

Author keywords

3D integration; 3D packaging; Die bonding; Die stacking; Through silicon via (TSV)

Indexed keywords

EID: 84881786145     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1002/9783527623051.ch1     Document Type: Editorial

References (15)

1. Banerjee, K., Souri, S., Kapur, P. and Saraswat, K. (2001) 3D ICs: a novel chip design for improving deep sub-micron interconnect performance and subsystems-on-chip integration. Proceedings of IEEE, 89, 602.
2. Anthony, T. (1981) Forming electrical interconnection through semiconductor wafers. Journal of Applied Physics, 52, 5340.
3. Akasaka, Y. and Nishimura, T. (1986) Concept and basic technologies for 3D IC structure. IEDM Technical Digest, 488.
4. Kunio, T., Oyama, K., Hayashi, Y. and Morimote, M. (1989) 3D Ics having 4 stacked active device layers. IEDM Technical Digest, 837.
5. Takahashi, S., Hayashi, Y., Kunio, T. and Endo, N. (1992) Characteristics of thin film devices for a stacked type MCM. Proceedings IEEE MCMC, 159.
6. Bertin, C., Perlman, D. and Shanken, S. (1993) Evaluation of a 3-D memory cube system. IEEE Transactions CHMT, 16, 1006.
7. Gann, K. (1998) High density packaging of flash memory. Proceedings IEEE Int. Non Volatile Memory Technology Conference, p. 96.
8. Pinal, S. Tassleei, J. Lepinois, F. et al. (2001) Ultra thin chip verticle interconnect technique. Proceedings IMAPS Europe, p. 42.
9. Pinel, S. et al. (2002) Thermal modeling and management in ultrathin chip stack technology. IEEE Transactions CPMT, 25, 244.
10. European Patent UTCS EP 992011061.
11. Fujitsu press release July 15th 2002 at Semicon West.
12. Reichl, H., Ostermann, A.,Weiland, R. and Ramm, P. (2003) The 3rd dimension in microelectronic packaging. Proceedings 14th European Micro & Packaging Conf. Friedrichshafen GR, p. 1.
13. Ostmann, A. et al. (2005) Technology for embedding active die. Proceedings European Microelectronic Packaging Conference, Brugge BE, p. 101.
14. Souriau, J.C, Lignier, O., Charrier, M. and Poupon, G. (2005) Wafer level processing of 3D system in package for Rf and data applications. Proceedings Electronic Component and Technology Conference, p. 356.
15. Imoto, T. et al. (2001) Development of 3-dimensional module package, system module block. Proceedings 51st Elect. Component Technology Conference, Orlando, p. 552.