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Volumn 5, Issue 19, 2013, Pages 8968-8972

A facile route to Si nanowire gate-all-around field effect transistors with a steep subthreshold slope

(6) Lee, Jae Hyun a,b,c Kim, Byung Sung a,b,c Choi, Soon Hyung b,c Jang, Yamujin b,c Hwang, Sung Woo c Whang, Dongmok a,b,c

a Sungkyunkwan University (South Korea)

b Sungkyunkwan University (South Korea)

c Samsung Advanced Institute of Technology (SAIT) (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DEPOSITION PROCESS; DEVICE APPLICATION; FIELD EFFECT TRANSISTOR (FETS); INTERFACE TRAPPED CHARGES; ONE-STEP WET ETCHINGS; SOURCE-DRAIN CONTACTS; SUBTHRESHOLD SLOPE; THERMAL OXIDATION;

DIGITAL DEVICES; FIELD EFFECT TRANSISTORS; GALLIUM ALLOYS; GATE DIELECTRICS; NANOWIRES; SHELLS (STRUCTURES);

SILICON;

EID: 84884255591 PISSN: 20403364 EISSN: 20403372 Source Type: Journal
DOI: 10.1039/c3nr02552g Document Type: Article

Times cited : (11)

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