A 1.8-V 128-Mb 125-MHz multilevel cell flash memory with flexible read while write

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 11, 2003, Pages 1929-1933

  Elmhurst, Daniel ^a   Goldman, Matthew ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Active current mirror; Address transition detection (ATD); Amplifier; Drain biasing; Flash; Multilevel cell (MLC); Nonvolatile memory; NOR flash; Parallel sensing; Read while write (RWW); Serial sensing

Indexed keywords

ALGORITHMS; AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; CELLULAR ARRAYS; LOGIC DESIGN; NONVOLATILE STORAGE; THRESHOLD VOLTAGE;

ACTIVE CURRENT MIRROR; ADDRESS TRANSITION DETECTION; DRAIN BIASING; FLEXIBLE READ WHILE WRITE; MUTILEVEL CELL FLASH MEMORY; PARALLEL SENSING; SERIAL SENSING;

FLASH MEMORY;

EID: 0242551719     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.818144     Document Type: Article

References (4)

1. M. Bauer et al., "A multilevel-cell 32 Mb flash memory," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1995, pp. 132-133.
2. B. Pathak et al., "A 1.8-V 100-MHz flexible read while write flash memory," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2001, pp. 32-33.
3. H. A. Castro et al., "A 125MHz burst mode 0.18 μm 128Mbit 2 bits per cell flash memory," in Symp. VLSI Circuits Dig. Tech. Papers, June 2002, pp. 304-307.
4. D. Elmhurst et al., "A 1.8-V 128-Mb 125-MHz multi-level cell flash memory with flexible read while write," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2003, pp. 286-287.