A multilevel read and verifying scheme for Bi-NAND flash memories

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 5, 2007, Pages 1180-1187

  Chung, Chiu Chiao ^b   Lin, Hongchin ^a,b   Lin, Yen Tai ^c  

^a IEEE   (Taiwan)

^b NATIONAL CHUNG HSING UNIVERSITY   (Taiwan)

^c EMEMORY TECHNOLOGY INC   (Taiwan)

Author keywords

Bi NAND; Dichotomous; Flash memory; Mismatch; Multilevel; Negative programmed threshold voltage; Read verifying

Indexed keywords

DICHOTOMOUS ARCHITECTURE; NEGATIVE PROGRAMMED THRESHOLD VOLTAGE;

AMPLIFIERS (ELECTRONIC); DATA STORAGE EQUIPMENT; ELECTRIC POWER UTILIZATION; NAND CIRCUITS; THRESHOLD VOLTAGE; VERIFICATION;

FLASH MEMORY;

EID: 34247330967     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.894822     Document Type: Conference Paper

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