The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 5, Issue 4, 1997, Pages 360-368

  Eisele, Martin ^a,b,c   Berthold, Jörg ^c   Schmitt Landsiedel, Doris ^b   Mahnkopf, Reinhard ^c  

^a IEEE   (Germany)

^b TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^c SIEMENS AG   (Germany)

Author keywords

Gate delay variations; Low voltage digital design; Parameter variations; Path delay variations; Pipelined circuits; Scaling; SRAM; V th variations; Yield

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; RANDOM ACCESS STORAGE; TIMING CIRCUITS;

INTRA DIE DEVICE PARAMETER VARIATIONS; STATIC RANDOM ACCESS MEMORY (SRAM);

DIGITAL INTEGRATED CIRCUITS;

EID: 0031342511     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.645062     Document Type: Article

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