-
1
-
-
13144266757
-
A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies
-
Jan
-
A. Agarwal et al. A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies. IEEE Transactions on VLSI Systems, 13(1), Jan. 2005.
-
(2005)
IEEE Transactions on VLSI Systems
, vol.13
, Issue.1
-
-
Agarwal, A.1
-
2
-
-
34247235826
-
-
amber (1) manual page. BSD General Commands Manual, Dec. 2005.
-
amber (1) manual page. BSD General Commands Manual, Dec. 2005.
-
-
-
-
4
-
-
0041633858
-
Parameter Variations and Impact on Circuits and Microarchitecture
-
June
-
S. Borkar et al. Parameter Variations and Impact on Circuits and Microarchitecture. In DAC '03: Proc. of the 40th Design Automation Conf., June 2003.
-
(2003)
DAC '03: Proc. of the 40th Design Automation Conf
-
-
Borkar, S.1
-
5
-
-
0034316092
-
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors
-
Nov/Dec
-
D. Brooks et al. Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. IEEE Micro, 20(6):26-44, Nov/Dec. 2000.
-
(2000)
IEEE Micro
, vol.20
, Issue.6
, pp. 26-44
-
-
Brooks, D.1
-
11
-
-
0024012163
-
Reevaluating Amdahl's Law
-
May
-
J. L. Gustafson. Reevaluating Amdahl's Law. Communications of the ACM, 31(5):532-533, May 1988.
-
(1988)
Communications of the ACM
, vol.31
, Issue.5
, pp. 532-533
-
-
Gustafson, J.L.1
-
12
-
-
0034226001
-
Measuring CPU Performance in the New Millennium
-
July
-
J. L. Henning. SPEC CPU2000: Measuring CPU Performance in the New Millennium. IEEE Computer, 33(7):28-35, July 2000.
-
(2000)
IEEE Computer
, vol.33
, Issue.7
, pp. 28-35
-
-
Henning, J.L.1
CPU, S.P.E.C.2
-
15
-
-
0036045542
-
An Integer Linear Programming Based Approach for Parallelizing Applications in On-Chip Multiprocessors
-
June
-
I. Kadayif, M. Kandemir, and U. Sezer. An Integer Linear Programming Based Approach for Parallelizing Applications in On-Chip Multiprocessors. In DAC '02: Proc. of the 39th Design Automation Conf., June 2002.
-
(2002)
DAC '02: Proc. of the 39th Design Automation Conf
-
-
Kadayif, I.1
Kandemir, M.2
Sezer, U.3
-
17
-
-
85008065233
-
Processor Power Reduction via Single-ISA Heterogeneous Multicore Architectures
-
Apr
-
R. Kumar et al. Processor Power Reduction via Single-ISA Heterogeneous Multicore Architectures. Computer Architecture Letters, Apr. 2003.
-
(2003)
Computer Architecture Letters
-
-
Kumar, R.1
-
24
-
-
34247241787
-
-
Massively Parallel Technologies
-
Massively Parallel Technologies. http://www.massivelyparallel.com/, 2006.
-
(2006)
-
-
-
26
-
-
0032683935
-
Environment for PowerPC Microarchitecture Exploration
-
May/June
-
M. Moudgill, J.-D. Wellman, and J. H. Moreno. Environment for PowerPC Microarchitecture Exploration. IEEE Micro, 19(3):15-25, May/June 1999.
-
(1999)
IEEE Micro
, vol.19
, Issue.3
, pp. 15-25
-
-
Moudgill, M.1
Wellman, J.-D.2
Moreno, J.H.3
-
27
-
-
34247256935
-
Dynamically Optimized Power Efficiency with Foxton Technology
-
Aug
-
S. Naffziger. Dynamically Optimized Power Efficiency with Foxton Technology. In Proc. of Hot Chips 17, Aug. 2005.
-
(2005)
Proc. of Hot Chips
, vol.17
-
-
Naffziger, S.1
-
31
-
-
1442343731
-
-
Computer Sciences Department, Temple University MS:, Oct
-
Y. Shi. Reevaluating Amdahl's Law and Gustafson's Law. Computer Sciences Department, Temple University (MS:38-24), Oct. 1996.
-
(1996)
Reevaluating Amdahl's Law and Gustafson's Law
, pp. 38-24
-
-
Shi, Y.1
-
34
-
-
0038528639
-
Effectiveness of Adaptive Supply Voltage and Body Bias for Reducing Impact of Parameter Variations in Low Power and High Performance Microprocessors
-
May
-
J. Tschanz et al. Effectiveness of Adaptive Supply Voltage and Body Bias for Reducing Impact of Parameter Variations in Low Power and High Performance Microprocessors. IEEE Journal of Solid-State Circuits, 38(5), May 2003.
-
(2003)
IEEE Journal of Solid-State Circuits
, vol.38
, Issue.5
-
-
Tschanz, J.1
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