Practical strategies for power-efficient computing technologies

Proceedings of the IEEE

Volumn 98, Issue 2, 2010, Pages 215-236

  Chang, Leland ^a   Frank, David J ^a   Montoye, Robert K ^a   Koester, Steven J ^a   Ji, Brian L ^a,b   Coteus, Paul W ^a   Dennard, Robert H ^a   Haensch, Wilfried ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b NONE   (United States)

Author keywords

Circuit optimization; CMOS digital integrated circuits; CMOSFETs; Integrated circuit design; Integrated circuit interconnections; Parallel machines; Power distribution

Indexed keywords

CACHE MEMORY; COMPUTATION THEORY; DIGITAL INTEGRATED CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; EFFICIENCY; ELECTRIC POWER TRANSMISSION; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC DEVICES; MICROELECTRONICS; SUPERCOMPUTERS; VOLTAGE SCALING;

CIRCUIT OPTIMIZATION; CMOS DIGITAL INTEGRATED CIRCUITS; CMOSFETS; INTEGRATED CIRCUIT INTERCONNECTIONS; PARALLEL MACHINE; POWER DISTRIBUTIONS;

COMPUTER ARCHITECTURE;

EID: 75649121827     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2009.2035451     Document Type: Article

References (69)

1. G. E. Moore, "Progress in digital integrated electronics, "in IEDM Tech. Dig., 1975, pp. 11-13.
2. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, "Design of ion-implanted MOSFETs with very small physical dimensions, "IEEE J. Solid-State Circuits, vol.SC-9, pp. 256-268, Oct. 1974.
3. D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies, "Proc. IEEE, vol.89, pp. 259-288, Mar. 2001.
4. A. P. Chandrasakan, S. Sheng, and R. W. Broderson, "Low-power CMOS digital design, "IEEE J. Solid-State Circuits, vol.27, pp. 473-483, Apr. 1992.
5. M. Horowitz, T.Indermauer, and R. Gonzalez, "Low-power digital design, "in IEEE Symp. Low Power Electron., 1994, pp. 8-11.
6. J. Meindl, "Low power microelectronics: Retrospect and prospect, "Proc. IEEE, vol.83, pp. 619-635, Apr. 1995.
7. M. Horowitz and W. Dally, "How scaling will change processor architecture, "in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2004, pp. 132-133.
8. J. Tschanz, S. Narendra, Y. Ye, B. Bloechel, S. Borker, and V. De, "Dynamic-sleep transistor and body bias for active leakage power control of microprocessors, "in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2003, pp. 102-103.
9. K. Rajamani, C. Lefurgy, S. Ghiasi, J. Rubio, H. Hanson, and T. Keller, "Power management solutions for computer systems and datacenters, "in Tutorial in Proc. Int. Symp. High-Performance Comput. Archit., 2008.
10. G. Baccarani, M. R. Wordeman, and R. H. Dennard, "Generalized scaling theory and its application to a 1/4 micrometer MOSFET design, "IEEE Trans. Electron Devices, vol.ED-31, pp. 452-462, Apr. 1984.
11. E. J. Nowak, "Maintaining the benefits of CMOS scaling when scaling bogs down, "IBM J. Res. Dev., vol.46, pp. 169-180, Mar./May 2002.
12. R. H. Dennard, J. Cai, and A. Kumar, BA perspective on today's scaling challenges and possible future directions, "Solid-State Electron., vol. 51, pp. 518-525, Apr. 2007.
13. D. J. Frank, W. Haensch, G. Shahidi, and O. Dokumaci, "Optimizing CMOS technology for maximum performance, "IBM J. Res. Dev., vol. 50, no. 4/5, pp. 419-431, Jul./Sep. 2006.
14. C. Wann, R. Wong, D. J. Frank, R. Mann, S.-B. Ko, P. Croce, D. Lea, D. Hoyniak, Y.-M. Lee, J. Toomey, M. Weybright, and J. Sudijono, "SRAM cell design for stability methodology, "in Proc. IEEE VLSI-TSA Int. Symp. VLSI Technol., 2005, pp. 21-22.
15. V. Zyuban and P. Strenski, "Unified method for resolving power-performance tradeoffs at the microarchitectural and circuit levels, "in Proc. Int. Symp. Low Power Electron. and Design, 2002, pp. 166-171.
16. G. M. Amdahl, "Validity of the single-processor approach to achieving large-scale computing capabilities, "in Proc. Amer. Federation Inf. Process. Soc. Conf., 1967, pp. 483-485, AFIPS Press.
17. J. L. Gustafson, "Reevaluating Amdahl's law, "Commun. ACM, vol.31, pp. 532-533, May 1988.
18. R. Gonzalez, B. M. Gordon, and M. A. Horowitz, "Supply and threshold voltage scaling for low power CMOS, "IEEE J. Solid-State Circuits, vol. 32, pp. 1210-1216, Aug. 1997.
19. S. Hanson, ". Zhai, K. Berstein, D. Blaauw, A. Bryant, L. Chang, K. K. Das, W. Haensch, E. J. Nowak, and D. M. Sylvester, "Ultralow-voltage, minimum-energy CMOS, "IBM J. Res. Dev., pp. 469-490, Jul./Sep. 2006.
20. D. J. Frank, Y. Taur, and H.-S. P. Wong, "Generalized scale length for two-dimensional effects in MOSFET's, "IEEE Electron Device Lett., vol.19, pp. 385-387, Oct. 1998.
21. R. W. Keyes, "Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics, "IEEE J. Solid-State Circuits, vol.SC-10, pp. 245-247, Aug. 1975.
22. J. Pille, C. Adams, T. Christensen, S. Cottier, S. Ehrenreich, T. Kono, D. Nelson, O. Takahashi, S. Tokito, O. Torreiter, O. Wagner, and D. Wendel, "Implementation of the CELL broadband engine in a 65 nm SOI technology featuring dual-supply SRAM arrays supporting 6 GHz at 1.3 V, "in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2007, pp. 322-323.
23. DD and dynamic power rails, "in Proc. Symp. VLSI Circuits Dig., 2004, pp. 292-293.
24. M. Khellah, Y. Ye, N. S. Kim, D. Somasekhar, G. Pandya, A. Farhang, K. Zhang, C. Webb, and V. De, "Wordline and bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65 nm CMOS designs, "in Proc. Symp. VLSI Circuits Dig., 2006, pp. 9-10.
25. H. Pilo, J. Barwin, G. Braceras, C. Browning, S. Burns, J. Gabric, S. Lamphier, M. Miller, A. Roberts, and F. Towler, "An SRAM design in 65 nm and 45 nm technology nodes featuring read and write-assist circuits to expand operating voltage, "in Symp. VLSI Circuits Dig., 2006, pp. 15-16.
26. L. Chang, R. K. Montoye, Y. Nakamura, K. A. Batson, R. J. Eickemeyer, R. H. Dennard, W. Haensch, and D. Jamsek, "An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches, "IEEE J. Solid-State Circuits, vol.43, pp. 956-963, Apr. 2008.
27. N. Verma and A. Chandrakasan, "A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy, "IEEE J. Solid-State Circuits, vol.43, pp. 141-149, Jan. 2008.
28. Y. Morita, H. Fujiwara, H. Noguchi, Y. Iguchi, K. Nii, H. Kawaguchi, and M. Yoshimoto, "An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment, "in Symp. VLSI Circuits Dig., 2007, pp. 256-257.
29. L. Chang, Y.-K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T.-J. King, "Extremely scaled silicon nano-CMOS devices, "Proc. IEEE, vol.91, pp. 1860-1873, Nov. 2003.
30. H. Kawasaki, M. Khater, M. Guillorn, N. Fuller, J. Chang, S. Kanakasabapathy, L. Chang, R. Muralidhar, K. Babich, Q. Yang, J. Ott, D. Klaus, E. Kratschmer, E. Sikorski, R. Miller, R. Viswanathan, Y. Zhang, J. Silverman, Q. Ouyang, A. Yagishita, M. Takayanagi, W. Haensch, and K. Ishimaru, BDemonstration of highly scaled FinFET SRAM cells with high-k/metal gate and investigation of characteristic variability for the 32 nm node and beyond, "in IEDM Tech. Dig., 2008, pp. 237-240.
31. M. Guillorn, J. Chang, A. Bryant, N. Fuller, O. Dokumaci, X. Wang, J. Newbury, K. Babich, J. Ott, ". Haran, R. Yu, C. Lavoie, D. Klaus, Y. Zhang, E. Sikorski, W. Graham, ". To, M. Lofaro, J. Tornello, D. Koli, ". Yang, A. Pyzyna, D. Neumeyer, M. Khater, A. Yagishita, H. Kawasaki, and W. Haensch, "FinFET performance advantage at 22 nm: An AC perspective, "in Symp. VLSI Technol. Dig., 2008, pp. 12-13.
32. T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, "IEEE J. Solid-State Circuits, vol.25, pp. 584-594, Apr. 1990.
33. G. Patounakis, Y. W. Li, and K. L. Shepard, "A fully integrated on-chip DC-DC conversion and power management system, "IEEE J. Solid-State Circuits, vol.39, pp. 443-451, Mar. 2004.
34. G. Wang, K. Cheng, H. Ho, J. Faltermeier, W. Kong, H. Kim, J. Cai, C. Tanner, K. McStay, K. Balasubramanyam, C. Pei, L. Ninomiya, X. Li, K. Winstel, D. Dobuzinsky, M. Naeem, R. Zhang, R. Deschner, M. J. Brodsky, S. Allen, J. Yates, Y. Feng, P. Marchetti, C. Noris, D. Casarotto, J. Benedict, A. Kniffin, D. Parise,B. Khan, J. Barth, P. Parries, T. Kirihata, J. Norum, and S. S. Iyer, "A 0.127/im high performance 65 nm SOI-based embedded DRAM for on-processor applications, "in IEDM Tech. Dig., 2006.
35. W. K. Luk and R. H. Dennard, "Gated diode amplifiers, "IEEE Trans. Circuits and Systems II: Express Briefs, vol.52, no.5, pp. 266-270, May 2005.
36. S. J. Koester, A. M. Young, R. R. Yu, S. Purushothaman, K.-N. Chen, D.C. La Tulipe, Jr., N. Rana, L. Shi, M. R. Wordeman, and E. J. Sprogis, BWafer-level 3D integration technology, "IBM J. Res. Dev., vol. 52, pp. 583-597, 2008.
37. P. S. Andry, C. K. Tsang, B. C. Webb, E. J. Sprogis, S. L. Wright, B. Dang, and D. G. Manzer, "Fabrication and characterization of robust through-silicon vias for silicon-carrier applications, "IBM J. Res. Dev., vol.52, pp. 571-581, 2008.
38. R. Palmer, J. Poulton, W. J. Dally, J. Eyles, A. M. Fuller, T. Greer, M. Horowitz, M. Kellam, F. Quan, and F. Zarkeshvari, "A 14 mW 6.25 Gb/s transceiver in 90 nm CMOS for serial chip-to-chip communications, "in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2007, pp. 440-441.
39. Y. Liu, B. Kim, T. O. Dickson, J. F. Bulzacchelli, and D. J. Friedman, "A 10 Gb/s compact low-power serial I/O with DFE-IIR equalization in 65 nm CMOS, "in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2009, pp. 182-183.
40. Y. Hidaka, W. Gai, T. Horie, J. H. Jiang, Y. Koyanagi, and H. Osone, "A 4-channel 10.3 Gb/s backplane transceiver macro with 35 dB equalizer and sign-based zero-forcing adaptive control, "in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2009, pp. 188-189.
41. J. F. Bulzacchelli, T. O. Dickson, Z. T. Deniz, H. A. Ainspan, ". D. Parker, M. P. Beakes, S. V. Rylov, and D. J. Friedman, "A 78 mW 11.1 Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65 nm CMOS, "in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), 2009, pp. 368-369.
42. D. A. B. Miller, "Rationale and challenges for optical interconnects to electronic chips, "Proc. IEEE, vol.88, pp. 728-749, Jun. 2000.
43. Joint Electron Devices Engineering Council.
44. [Online]. Available: http://www.jedec.org/
45. BBlue Gene, "IBM J. Res. Dev., vol. 49, Mar./May 2005, entire issue.
46. IBM Blue Gene Team, Overview of the IBM Blue Gene/P project, "IBM J. Res. Dev., vol. 52, pp. 199-220, Jan./Mar. 2008.
47. The Green500 List.
48. [Online]. Available: http://www.green500.org/
49. TOP500 Supercomputing Sites.
50. [Online]. Available: http://www.top500.org/
51. I. Yang, C. Vieri, A. Chandrakasan, and D. Antoniadis, "Backgated CMOS on SOIAS for dynamic threshold voltage control, "IEEE Trans. Electron Devices, vol.44, pp. 822-831, May 1997.
52. S. Salahuddin and S. Datta, "Use of negative capacitance to provide voltage amplification for low power nanoscale devices, "Nanoletters, vol.8, pp. 405-410, Feb. 2008.
53. K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, "I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q, "in IEDM Tech. Dig., 2002, pp. 289-292.
54. A. Padilla, C. W. Yeung, C. Shin, C. Hu, and T.-J. K. Liu, "Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages, "in IEDM Tech. Dig., 2008, pp. 171-174.
55. W. Y. Choi, B.G. Park, J. D. Lee, and T.-J. King Liu, "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, "IEEE Electron Device Lett., vol. 28, pp. 743-745, Aug. 2007.
56. O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt, and D. A. Antoniadis, "Design of tunneling field-effect transistors using strained-silicon/strained-germanium type-II staggered heterojunctions, "IEEE Electron Device Lett., vol.29, pp. 1074-1077, Sep. 2008.
57. C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck, and J. L. A. van de Snepscheut, "Hot-clock nMOS, "in Proc. 1985 Chapel Hill Conf. VLSI, 1985, pp. 1-17.
58. J. S. Hall, "An electroid switching model for reversible computer architectures, "in Proc. Workshop Physics Comput., 1992, pp. 237-247.
59. J. G. Koller and W. C. Athas, "Adiabatic switching, low energy computing, and physics of storing and erasing information, "in Proc. Workshop Physics Comput., 1992, pp. 267-270.
60. S. G. Younis and T. F. Knight, Jr., "Practical implementation of charge recovering asymptotically zero power CMOS, "in Proc. 1993 Symp. Integr. Syst., 1993, pp. 234-250.
61. P. Solomon and D. J. Frank, "The case for reversible computation, "in Proc. Int. Workshop Low Power Design, 1994, pp. 93-98.
62. J. S. Denker, S. C. Avery, A. G. Dickinson, A. Kramer, and T. R. Wik, "Adiabatic computing with the 2N-2N2D logic family, "in Proc. Int. Workshop Low Power Design, 1994, pp. 183-187.
63. D. J. Frank and P. M. Solomon, BElectroid-oriented adiabatic switching circuits, "in Proc. Int. Workshop Low Power Design, 1995, pp. 197-202.
64. D. J. Frank, "Comparison of high speed voltage-scaled conventional and adiabatic circuits, "in Proc. Int. Workshop Low Power Electron. Design, 1996, pp. 377-380.
65. W. Athas, "Practical considerations of clock-powered logic, "in Proc. Int. Workshop Low Power Electron. Design, 2000, pp. 173-178.
66. R. Landauer, "Irreversibility and heat generation in the computing process, "IBM J. Res. Dev., vol.5, pp. 183-191, 1961.
67. C. H. Bennett, "Logical reversibility of computation, "IBM J. Res. Dev., vol.6, pp. 525-532, 1973.
68. M. P. Frank, "Introduction to reversible computing: Motivation, progress, and challenges, "in Proc. 2nd Conf. Comput. Frontiers, 2005, pp. 385-390.
69. D. F. Heidel, K. P. Rodbell, E. H. Cannon, C. Cabral, Jr., M. S. Gordon, P. Oldiges, and H. H. K. Tang, "Alpha-particle-induced upsets in advanced CMOS circuits and technology, "IBM J. Res. Dev., vol.52, pp. 225-232, 2008.