Intrinsic correlation between PBTI and TDDB degradations in nMOS HK/MG dielectrics

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2012, Pages

  Yang, Jiaqi ^a,c   Masuduzzaman, Muhammad ^a   Joshi, Kaustubh ^b   Mukhopadhyay, Subhadeep ^b   Kang, Jinfeng ^c   Mahapatra, Souvik ^b   Alam, Muhammad A ^a  

^a PURDUE UNIVERSITY   (United States)

^b INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^c PEKING UNIVERSITY   (China)

Author keywords

positive bias temperature instability (PBTI); structual relaxation; time dependent dielectric breakdown (TDDB); trap generation

Indexed keywords

CMOS TECHNOLOGY; DIELECTRIC RELIABILITY; GATE STACKS; MEASURED PARAMETERS; PHENOMENOLOGICAL THEORY; POSITIVE BIAS TEMPERATURE INSTABILITIES; RELAXATION ENERGIES; STRESS-INDUCED LEAKAGE CURRENT; STRUCTUAL RELAXATION; TIME DEPENDENT DIELECTRIC BREAKDOWN; TIME EVOLUTIONS; TRAP GENERATION; VOLTAGE DEPENDENCE;

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; RELIABILITY;

DIELECTRIC MATERIALS;

EID: 84866597235     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2012.6241855     Document Type: Conference Paper

References (32)

1. A. Kerber and E. Cartier, "Reliability Challenges for CMOS Technology Qualifications with Hafnium Oxide/Titanium Nitride Gate Stacks," IEEE Trans. Device Mater. Rel., vol. 9, no. 2, pp. 147-162, 2009.
2. 2/TiN Gate Stacks," IEEE Trans. Device Mater. Rel., vol. 9, no. 2, pp. 128-134, 2009.
3. G. Bersuker et al., "Breakdown in the Metal/High-k Gate Stack: Identifying the 'Weak Link' in the Multilayer Dielectric," in IEDM Tech. Dig., 2008, pp. 791-794.
4. 2 Layer," in Proc. Int. Rel. Phys. Symp., 2010, pp. 373-378.
5. X. Garros et al., "PBTI Mechanisms in La Containing Hf-Based Oxides Assessed by Very Fast IV Measurements," in IEDM Tech. Dig., 2010, pp. 90-93.
6. 2/TiN Gate Stacks during Positive-Bias Temperature Stress," in Proc. Int. Rel. Phys. Symp., 2009, pp. 486-492.
7. J. Q. Yang, M. Masuduzzman, J. F. Kang, and M. A. Alam, "SILC-Based Reassignment of Trapping and Trap Generation Regimes of Positive Bias Temperature Instability," in Proc. Int. Rel. Phys. Symp., 2011, pp. 196-201.
8. A. Kerber, E. Cartier, B. P. Linder, S. A. Krishnan, and T. Nigam, "TDDB Failure Distribution of Metal Gate/High-k CMOS Devices on SOI Substrates," in Proc. Int. Rel. Phys. Symp., 2009, pp. 505-509.
9. T. Nigam, A. Kerber, and P. Peumans, "Accurate Model for Time-Dependent Dielectric Breakdown of High-k Metal Gate Stacks," in Proc. Int. Rel. Phys. Symp., 2009, pp. 523-530.
10. T. Kauerauf et al., "Methodologies for Sub-1nm EOT TDDB Evaluation," in Proc. Int. Rel. Phys. Symp., 2011, pp. 7-16.
11. J. Sune, S. Tous, and E. Miranda, "Gate Stack Insulator Breakdown when the Interface Layer Thickness is Scaled toward Zero," Appl. Phys. Lett., vol. 97, no. 21, p. 213503, 2010.
12. 2/High-K Stacks," in Proc. Int. Rel. Phys. Symp., 2006, pp. 82-89.
13. D. Varghese et al., "Off-State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown," IEEE Trans. Electron Devices, vol. 54, no. 10, pp. 2669-2678, 2007.
14. M. A. Alam, "Negative Bias Temperature Instability Basics/Modeling," in Proc. Int. Rel. Phys. Symp., 2005, tutorial.
15. BD in Ultrathin Oxides," IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 226-231, 2002.
16. S. Takagi, N. Yasuda, and A. Toriumi, "A New I-V Model for Stress-Induced Leakage Current Including Inelastic Tunneling," IEEE Trans. Electron Devices, vol. 46, no. 2, pp. 348-354, 1999.
17. Chih-Tang Sah, A. Neugroschel, K. M. Han, and J. T. Kavalieros, "Profiling Interface Traps in MOS Transistors by the DC Current-Voltage Method," IEEE Electron Device Lett., vol. 17, no. 2, pp. 72-74, 1996.
18. BD Power-Law for Voltage Dependence of Oxide Breakdown in Ultrathin Gate Oxides," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2244-2253, 2002.
19. 2 under Long-Term/Low-Field Test Conditions," in IEDM Tech. Dig., 1998, pp. 171-174.
20. 2 Calculated with Periodic and Embedded Cluster Density Functional Theory," Phys. Rev. B (Condensed Matter and Materials Physics), vol. 75, no. 20, p. 205336, 2007.
21. R. Degraeve et al., "Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A Quantitative Electrical Technique for Studying Defects in Dielectric Stacks," in IEDM Tech. Dig., 2008, pp. 1-4.
22. M. Masuduzzaman, A. Islam, R. Degraeve, Moonju Cho, M. Zahid, and M. Alam, "Experimental Identification of Unique Oxide Defect Regions by Characteristic Response of Charge Pumping," in Proc. Int. Rel. Phys. Symp., 2011, pp. 207-212.
23. M. A. Alam, B. E. Weir, and P. J. Silverman, "A Study of Soft and Hard Breakdown - Part I: Analysis of Statistical Percolation Conductance," IEEE Trans. Electron Devices, vol. 49, no. 2, pp. 232-238, 2002.
24. J. Sune, S. Tous, and E. Y. Wu, "Analytical Cell-Based Model for the Breakdown Statistics of Multilayer Insulator Stacks," IEEE Electron Device Lett., vol. 30, no. 12, pp. 1359-1361, 2009.
25. M. A. Alam, B. E. Weir, P. J. Silverman, Y. Ma, and D. Hwang, "The Statistical Distribution of Percolation Resistance as a Probe into the Mechanics of Ultra-Thin Oxide Breakdown," in IEDM Tech. Dig., 2000, pp. 529-532.
26. J. Huang et al., "Gate First High-k/Metal Gate Stacks with Zero SiOx Interface Achieving EOT=0.59nm for 16nm Application," in VLSI Symp. Tech. Dig., 2009, pp. 34-35.
27. W. L. Chang, J. H. Stathis, and E. Cartier, "Role of Interface Layer in Stress-Induced Leakage Current in High-k/Metal-Gate Dielectric Stacks," in Proc. Int. Rel. Phys. Symp., 2010, pp. 787-791.
28. S. A. Krishnan, E. Cartier, J. Stathis, M. Chudzik, and A. Kerber, "Mechanistic Understanding of Breakdown and Bias Temperature Instability in High-K Metal Devices Using Inline Fast Ramped Bias Test," in Proc. Int. Rel. Phys. Symp., 2011, pp. 387-391.
29. M. A. Alam, J. Bude, and A. Ghetti, "Field Acceleration for Oxide Breakdown-Can An Accurate Anode Hole Injection Model Resolve the E vs. 1/E Controversy?," in Proc. Int. Rel. Phys. Symp., 2000, pp. 21-26.
30. B. E. Weir, M. A. Alam, J. D. Bude, P. J. Silverman, A. Ghetti, F. Baumann, P. Diodato, D. Monroe, T. Sorsch, G. L. Timp, Y. Ma, M. M. Brown, A. Hamad, D. Hwang, and P. Mason, "Gate Oxide Reliability Projection to the Sub-2 nm Regime," Semicond. Sci. Technol., vol. 15, no. 5, pp. 455-461, 2000.
31. M. A. Alam, J. Bude, B. Weir, P. Silverman, A. Ghetti, D. Monroe, K. P. Cheung, and S. Moccio, "An Anode Hole Injection Percolation Model for Oxide Breakdown-the 'Doom's Day' Scenario Revisited," in IEDM Tech. Dig., 1999, pp. 715-718.
32. 2 Stacks," in VLSI Symp. Tech. Dig., 2004, pp. 140-141.