Role of interface layer in stress-induced leakage current in high-k/metal-gate dielectric stacks

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2010, Pages 787-791

  Chang, W L ^a   Stathis, J H ^b   Cartier, E ^b  

^a IBM MICROELECTRONICS   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Component; High k dielectrics; SILC; TDDB

Indexed keywords

COMPONENT; CONSTANT VOLTAGE STRESS; GATE DIELECTRIC STACKS; GATE TRANSISTORS; HIGH-K DIELECTRIC; INTERFACE LAYER; SILC; STRESS-INDUCED LEAKAGE CURRENT; TDDB;

GATE DIELECTRICS; GATES (TRANSISTOR); RELIABILITY; SILICA;

DIELECTRIC MATERIALS;

EID: 77957927255     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2010.5488732     Document Type: Conference Paper

References (10)

1. C. Prasad et al., IRPS 2008, p. 667;
2. S. Pae et al., IRPS 2009, p. 499.
3. E. Cartier and A. Kerber, IRPS 2009, p. 486.
4. G. Ribes et al., IRPS 2005, p. 61.
5. C. Young et al., IPRS 2006, p. 169.
6. G. Bersuker et al., IRPS 2007, p. 49;
7. IEDM 2008, pp. 791.
8. T. Nigam, A. Kerber, and P. Peumans, IRPS 2009, p. 523.
9. B. Linder et al., IRPS 2009, p. 510.
10. W. Lai et al., IRPS 2004, p. 102.