Mechanistic understanding of breakdown and bias temperature instability in high-K metal devices using inline fast ramped bias test

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2011, Pages

  Krishnan, Siddarth A ^a   Cartier, Eduard ^a   Stathis, James ^a   Chudzik, Michael ^a   Kerber, Andreas ^b  

^a IBM   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

BTI; High K; Metal Gate; Ramped Bias; Reliability; TDDB

Indexed keywords

BTI; HIGH-K; METAL GATE; RAMPED BIAS; TDDB;

LOGIC GATES; RELIABILITY;

INTEGRATED CIRCUITS;

EID: 79959324125     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2011.5784504     Document Type: Conference Paper

References (9)

1. M. Chudzik et al, Symposium on VLSI Technology, pp 194-195, 2007
2. W. Henson et al, IEDM, pg : 1-4, Dec 2008
3. A. Kerber et al, IEEE EDL, vol 27, # 7, pg 609-611, 2006
4. A. Kerber et al, WODIM, June 2006
5. A. Kerber et al, IEEE EDL vol 30, # 12, pg 1347-1349, 2009
6. A. Kerber et al, IEEE TDMR, vol 9, # 2, pg 147-162, 2009
7. D. Ioannou et al, IRPS, pg 1044-1048, Apr 2010
8. J. Yugami et al, IWGI, pg 140-145, Nov. 2003
9. S. Tsujikawa et al, IEDM, pg 824-827, Dec 2005