Hardening techniques for MRAM-based nonvolatile latches and Logic

IEEE Transactions on Nuclear Science

Volumn 59, Issue 4 PART 1, 2012, Pages 1136-1141

  Lakys, Yahya ^a,b   Zhao, Weisheng S ^a,b   Klein, Jacques Olivier ^a,b   Chappert, Claude ^a,b  

^a UNIVERSITÉ PARIS SACLAY   (France)

^b CNRS   (France)

Author keywords

Magnetic RAM (MRAM); multicontext; nonvolatile; radiation hardness by design; SEU; Spintronics

Indexed keywords

MAGNETIC RAMS; MULTICONTEXT; NON-VOLATILE; RADIATION HARDNESS; SEU;

CMOS INTEGRATED CIRCUITS; DESIGN; HARDENING; HARDNESS; LOGIC CIRCUITS; MAGNETOELECTRONICS; RANDOM ACCESS STORAGE;

MRAM DEVICES;

EID: 84865369577     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2012.2195677     Document Type: Article

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