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Volumn 51, Issue 6 II, 2004, Pages 3811-3815

Sense amplifier based RADHARD flip flop design

Author keywords

Digital circuits; Radiation hardening (RADHARD); Registers; Sequential logic circuit fault tolerance; Single event effects (SEEs); Single event transients (SETs)

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; ELECTRIC POTENTIAL; FIELD EFFECT TRANSISTORS; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS;

EID: 11044223544     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.839149     Document Type: Conference Paper
Times cited : (13)

References (9)
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  • 2
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  • 4
    • 11044226909 scopus 로고    scopus 로고
    • Single event upset, hardness by design. the 'one generation penalty' challenge
    • Manhattan Beach, CA, 26-29
    • M. P. Baze, "Single event upset, hardness by design. The 'one generation penalty' challenge," in Proc. 14th Biennial Single Event Effects Symp., Manhattan Beach, CA, 26-29 2004.
    • (2004) Proc. 14th Biennial Single Event Effects Symp.
    • Baze, M.P.1
  • 5
    • 11044237285 scopus 로고    scopus 로고
    • Limitation of single event hardening techniques in deep submicron technologies
    • Manhattan Beach, CA, Apr. 26-29
    • J. Benedetto, "Limitation of single event hardening techniques in deep submicron technologies," in Proc. 14th Biennial Single Event Effects Symp., Manhattan Beach, CA, Apr. 26-29, 2004.
    • (2004) Proc. 14th Biennial Single Event Effects Symp.
    • Benedetto, J.1
  • 6
    • 11044231952 scopus 로고    scopus 로고
    • Flip flop design with self timed latching edge for radiation hardened application
    • Atlanta, CA, July 19-23
    • W. Wang and H. Gong, "Flip flop design with self timed latching edge for radiation hardened application," in Proc. 41st IEEE Nuclear and Space Radiation Effects Conf., Atlanta, CA, July 19-23, 2004.
    • (2004) Proc. 41st IEEE Nuclear and Space Radiation Effects Conf.
    • Wang, W.1    Gong, H.2
  • 7
    • 0032070396 scopus 로고    scopus 로고
    • A reduced clock swing flip flop for 63% power reduction
    • May
    • H. Kawaguchi and T. Sakurai, "A reduced clock swing flip flop for 63% power reduction," IEEE J. Solid State Circuits, vol. 33, pp. 807-811, May 1998.
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    • Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
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    • V. Stojanovic and V. G. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," IEEE J. Solid State Circuits, vol. 34, pp. 536-548, Apr. 1999.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.