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Volumn 6, Issue 4, 1998, Pages 563-567

Modeling and comparing CMOS implementations of the C-element

Author keywords

Asynchronous design; Delay; Digital complementary metal oxide semiconductor (CMOS); Energy dissipation

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER SIMULATION; CONTROL EQUIPMENT; ENERGY DISSIPATION;

EID: 0032296806     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.736128     Document Type: Article
Times cited : (108)

References (12)
  • 1
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    • G. Birtwistle and A. Davis, Eds. New York: Springer-Verlag
    • S. Furber, "Computing without clocks: Micropipelining the ARM processor," in Asynchronous Digital Circuit Design, G. Birtwistle and A. Davis, Eds. New York: Springer-Verlag, 1995, pp. 211-262.
    • (1995) Asynchronous Digital Circuit Design , pp. 211-262
    • Furber, S.1
  • 3
    • 0024683698 scopus 로고
    • Micropipelines
    • June
    • I. E. Sutherland, "Micropipelines," Commun. ACM, vol. 32, pp. 720-738, June 1989.
    • (1989) Commun. ACM , vol.32 , pp. 720-738
    • Sutherland, I.E.1
  • 5
    • 0030173207 scopus 로고    scopus 로고
    • Four-phase micropipeline latch control circuits
    • June
    • S. B. Furber and P. Day, "Four-phase micropipeline latch control circuits," IEEE Trans VLSI Syst., vol. 4, pp. 247-253, June 1996.
    • (1996) IEEE Trans VLSI Syst. , vol.4 , pp. 247-253
    • Furber, S.B.1    Day, P.2
  • 6
    • 0003418582 scopus 로고    scopus 로고
    • Ph.D. dissertation, Eindhoven Univ. Technol., The Netherlands, June
    • A. M. G. Peeters, Single-Rail Handshake Circuits, Ph.D. dissertation, Eindhoven Univ. Technol., The Netherlands, June 1996.
    • (1996) Single-Rail Handshake Circuits
    • Peeters, A.M.G.1
  • 9
    • 30244527478 scopus 로고
    • Parallel progress and asynchronous circuit design
    • G. Birtwistle and A. Davis, Eds. New York: Springer-Verlag
    • J. C. Ebergen, J. Segers, and I. Benko, "Parallel progress and asynchronous circuit design," in Asynchronous Digital Circuit Design, G. Birtwistle and A. Davis, Eds. New York: Springer-Verlag, 1995, pp. 51-103.
    • (1995) Asynchronous Digital Circuit Design , pp. 51-103
    • Ebergen, J.C.1    Segers, J.2    Benko, I.3
  • 11
    • 0006768956 scopus 로고
    • Formal progress transformations for VLSI circuit synthesis
    • E. W. Dijkstra, Ed. Reading, MA: Addison-Wesley
    • A. J. Martin, "Formal progress transformations for VLSI circuit synthesis," in Formal Development of Programs and Proofs E. W. Dijkstra, Ed. Reading, MA: Addison-Wesley, 1989, pp. 59-80.
    • (1989) Formal Development of Programs and Proofs , pp. 59-80
    • Martin, A.J.1
  • 12
    • 0026882866 scopus 로고
    • Beware the isochronic fork
    • June
    • K. v. Berkei, "Beware the isochronic fork," Integration, The VLSI J., vol. 13, pp. 103-128, June 1992.
    • (1992) Integration, The VLSI J. , vol.13 , pp. 103-128
    • Berkei, K.V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.