NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 7, 2012, Pages 994-1007

  Dong, Xiangyu ^a   Xu, Cong ^b   Xie, Yuan ^b   Jouppi, Norman P ^c  

^a QUALCOMM INC   (United States)

^b The Pennsylvania State University   (United States)

^c HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

Analytical circuit model; MRAM; NAND Flash; nonvolatile memory; phase change random access memory (PCRAM); resistive random access memory (ReRAM); spin torque transfer memory (STT RAM)

Indexed keywords

ANALYTICAL CIRCUIT MODELS; MRAM; NAND FLASH; NON-VOLATILE MEMORIES; PHASE CHANGE RANDOM ACCESS MEMORY; RANDOM ACCESS MEMORIES; SPIN-TORQUE-TRANSFER MEMORY (STT-RAM);

DESIGN; MAGNETIC STORAGE; MEMORY ARCHITECTURE; MRAM DEVICES; OPTIMIZATION;

RANDOM ACCESS STORAGE;

EID: 84862685650     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2012.2185930     Document Type: Article

References (47)

1. S. J. E. Wilton and N. P. Jouppi, "CACTI: An enhanced cache access and cycle time model," IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 677-688, May 1996.
2. S. Thoziyoor, et al., "CACTI 5.1 technical report," HP Labs, Palo Alto, CA, Tech. Rep. HPL-2008-20, 2008.
3. S. Raoux, et al., "Phase-change random access memory: A scalable technology," IBM J. Res. Development, vol. 52, nos. 4-5, pp. 465-479, Jul. 2008.
4. J. J. Yang, et al., "Memristive switching mechanism for metal/oxide/metal nanodevices," Nature Nanotechnol., vol. 3, no. 7, pp. 429-433, 2008.
5. Z. Wei, et al., "Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism," in Proc. IEDM, 2008, pp. 293-296.
6. Y. S. Chen, et al., "Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity," in Proc. IEDM, 2009, pp. 105-108.
7. M.-J. Lee, et al., "2-stack 1D-1R cross-point structure with oxide diodes as switch elements for high density resistance RAM applications," in Proc. IEEE IEDM, Dec. 2007, pp. 771-774.
8. W. C. Chien, et al., "Multi-level operation of fully CMOS compatible WOx resistive random access memory (RRAM)," in Proc. Int. Memory Workshop, 2009, pp. 228-229.
9. S.-S. Sheu, et al., "A 4Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160 ns MLC-access capability," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2011, pp. 200-202.
10. K.-J. Lee, et al., "A 90 nm 1.8V 512Mb diode-switch PRAM with 266 MB/s read throughput," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 150-162, Jan. 2008.
11. F. Pellizzer, et al., "Novel μTrench phase-change memory cell for embedded and stand-alone nonvolatile memory applications," in Proc. Int. Symp. VLSI Technol., 2004, pp. 18-19.
12. S. J. Ahn, et al., "Highly manufacturable high density phase change memory of 64Mb and beyond," in Proc. IEDM, 2004, pp. 907-910.
13. K.-H. Kim, et al., "Nanoscale resistive memory with intrinsic diode characteristics and long endurance," Appl. Phys. Lett., vol. 96, no. 5, pp. 053 106.1-053 106.3, 2010.
14. H. Y. Lee, et al., "Evidence and solution of over-RESET problem for HfOx based resistive memory with sub-ns switching speed and high endurance," in Proc. IEDM, 2010, pp. 19.7.1-19.7.4.
15. International Technology Roadmap for Semiconductors. (2010). Process Integration, Devices, and Structures Update [Online]. Available: http://www.itrs.net
16. C. W. Smullen, et al., "Relaxing non-volatility for fast and energyefficient STT-RAM caches," in Proc. Int. Symp. High Performance Comput. Architecture, Feb. 2011, pp. 50-61.
17. D.-C. Kau, et al., "A stackable cross point phase change memory," in Proc. IEEE IEDM, Dec. 2009, pp. 27.1.1-27.1.4.
18. Y.-C. Chen, et al., "An access-transistor-free (0T/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device," in Proc. IEDM, 2003, pp. 750-753.
19. C. Xu, et al., "Design implications of memristor-based RRAM cross-point structures," in Proc. Des. Autom. Test Eur., 2011, pp. 1-6.
20. S. Thoziyoor, et al., "A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies," in Proc. Int. Symp. Comput. Architecture, 2008, pp. 51-62.
21. International Technology Roadmap for Semiconductors. The Model for Assessment of CMOS Technologies and Roadmaps (MASTAR) [Online]. Available: http://www.itrs.net/models.html
22. A. Udipi, et al., "Rethinking DRAM design and organization for energy-constrained multi-cores," ACM SIGARCH Comput. Architecture News, vol. 38, no. 3, pp. 175-186, 2010.
23. J. Liang and H. S. P. Wong, "Cross-point memory array without cell selectors: Device characteristics and data storage pattern dependencies," IEEE Trans. Electron Devices, vol. 57, no. 10, pp. 2531-2538, Oct. 2010.
24. M. Hosomi, et al., "A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM," in Proc. IEDM, 2005, pp. 459-462.
25. T. Kawahara, et al., "2Mb spin-transfer torque RAM (SPRAM) with bit-by-bit bidirectional current write and parallelizing-direction current read," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2007, pp. 480-617.
26. K. Tsuchida, et al., "A 64Mb MRAM with clamped-reference and adequate-reference schemes," in Proc. Int. Solid-State Circuits Conf., 2010, pp. 268-269.
27. H.-R. Oh, et al., "Enhanced write performance of a 64-Mb phasechange random access memory," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 122-126, Jan. 2006.
28. S. Hanzawa, et al., "A 512 kB embedded phase change memory with 416 kB/s write throughput at 100μA cell write current," in Proc. Int. Solid-State Circuits Conf., 2007, pp. 474-616.
29. S. Kang, et al., "A 0.1μm 1.8V 256Mb phase-change random access memory (PRAM) with 66MHz synchronous burst-read operation," IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 210-218, Jan. 2007.
30. F. Fishburn, et al., "A 78nm 6F2 DRAM technology for multigigabit densities," in Proc. Symp. VLSI Technol., 2004, pp. 28-29.
31. J. H. Oh, et al., "Full integration of highly manufacturable 512Mb PRAM based on 90 nm technology," in Proc. IEDM, 2006, pp. 49-52.
32. Y. Zhang, et al., "An integrated phase change memory cell with Ge nanowire diode for cross-point memory," in Proc. IEEE Symp. VLSI Technol., Jun. 2007, pp. 98-99.
33. Y. Sasago, et al., "Cross-point phase change memory with 4F2 cell size driven by low-contact-resistivity poly-Si diode," in Proc. Symp. VLSI Technol., 2009, pp. 24-25.
34. I. E. Sutherland, R. F. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits. San Francisco, CA: Morgan Kaufmann, 1999.
35. M. A. Horowitz, "Timing models for MOS circuits," Stanford University, Stanford, CA, Tech. Rep. SEL-TR-83-003, 1983.
36. E. Seevinck, P. J. van Beers, and H. Ontrop, "Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's," IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 525-536, Apr. 1991.
37. Y. Moon, et al., "1.2V 1.6 Gb/s 56 nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture," in Proc. Int. Solid-State Circuits Conf., 2009, pp. 128-129.
38. G. W. Burr, et al., "Phase change memory technology," J. Vac. Sci. Technol. B, vol. 28, no. 2, pp. 223-262, 2010.
39. K. Ishida, et al., "A 1.8V 30 nJ adaptive program-voltage (20 V) generator for 3D-integrated NAND Flash SSD," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2009, pp. 238-239, 239a.
40. L. M. Grupp, et al., "Characterizing Flash memory: Anomalies, observations, and applications," in Proc. Int. Symp. Microarchitecture, 2009, pp. 24-33.
41. R. J. Evans and P. D. Franzon, "Energy consumption modeling and optimization for SRAMs," IEEE J. Solid-State Circuits, vol. 30, no. 5, pp. 571-579, May 1995.
42. M. Mamidipaka and N. Dutt, "eCACTI: An enhanced power estimation model for on-chip caches," Center Embedded Comput. Syst., Univ. California, Irvine, Tech. Rep. TR04-28, 2004.
43. N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, "Architecting efficient interconnects for large caches with CACTI 6.0," IEEE Micro, vol. 28, no. 1, pp. 69-79, Jan.-Feb. 2008.
44. X. Dong, et al., "Circuit and microarchitecture evaluation of 3-D stacking magnetic RAM (MRAM) as a universal memory replacement," in Proc. Des. Autom. Conf., 2008, pp. 554-559.
45. P. Mangalagiri, et al., "A low-power phase change memory based hybrid cache architecture," in Proc. Great Lakes Symp. VLSI, 2008, pp. 395-398.
46. X. Dong, N. P. Jouppi, and Y. Xie, "PCRAMsim: System-level performance, energy, and area modeling for phase-change RAM," in Proc. Int. Conf. Comput.-Aided Des., 2009, pp. 269-275.
47. V. Mohan, S. Gurumurthi, and M. R. Stan, "FlashPower: A detailed power model for NAND Flash memory," in Proc. Des. Autom. Test Eur., 2010, pp. 502-507.