1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages

  Moon, Yongsam ^a   Cho, Yong Ho ^a   Lee, Hyun Bae ^a   Jeong, Byung Hoon ^a   Hyun, Seok Hun ^a   Kim, Byung Chul ^a   Jeong, In Chul ^a   Seo, Seong Young ^a   Shin, Jun Ho ^a   Choi, Seok Woo ^a   Song, Ho Sung ^a   Choi, Jung Hwan ^a   Kyung, Kye Hyun ^a   Jun, Young Hyun ^a   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349280617     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977341     Document Type: Conference Paper

References (5)

1. Y.K. Kim, Y.J. Jeon, B.H. Jeong, et al., "A 1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAM with an Address Queuing Scheme and Bang-Bang Jitter Reduced DLL Scheme, " Dig. Symp. VLSI Circuits, pp. 182-183, Jun, 2007.
2. E. Seevinck, P.J. van Beers, H. Ontrop, "Current-Mode Techniques for High-Speed VLSI circuits with Application to Current Sense Amplifier for CMOS SRAM's" IEEE J. Solid-State Circuits, vol.26, no.4, pp. 525-536, Apr. 1991.
3. H. Fujisawa, S. Kubouchi, K. Kuroki, et al., "An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme, " IEEE J. of Solid-State Circuits, vol.42, no.1, pp. 201-209, Jan. 2007.
4. C. Park, H. Chung, Y-S. Lee, et al., "A 512-Mb DDR3 SDRAM Prototype with CIO Minimization and Self-Calibration Techniques, " IEEE J. of Solid-State Circuits, vol.41, no.4, pp. 831-841, Apr. 2006.
5. C-S. Kim, J-S. Kim, B-S. Kong, et al., "Presetting Pulse-Based Flip-Flop, " IEEE Int. Symp. Circuits and Systems, pp. 588-591, May 2008.