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Volumn , Issue , 2009, Pages 682-687

Performanace and reliability analysis of 3D-integration structures employing through silicon via (TSV)

Author keywords

3D integration; Carrier mobility; Design for manufacturability; Mechancial reliability; Thermomechanical stress

Indexed keywords

3D-INTEGRATION; BARRIER LAYERS; CRACK NUCLEATION; DESIGN FOR MANUFACTURABILITY; DEVICE PERFORMANCE; INDUCED STRESS; MATERIAL CHOICE; MECHANCIAL RELIABILITY; STRESS DISTRIBUTION; STRUCTURE RELIABILITY; THERMAL MISMATCH STRESS; THERMOMECHANICAL STRESS; THROUGH-SILICON-VIA;

EID: 70449088867     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2009.5173329     Document Type: Conference Paper
Times cited : (127)

References (6)
  • 3
    • 39749177820 scopus 로고    scopus 로고
    • Through Silicon Via and 3-D Wafer/Chip Stacking Technology
    • Digest of Technical Papers, 2006, pp
    • K. Takahashi and M. Sekiguchi, "Through Silicon Via and 3-D Wafer/Chip Stacking Technology," 2006 Symposium On VLSI Circuits, Digest of Technical Papers, 2006, pp. 89-92.
    • (2006) Symposium On VLSI Circuits , pp. 89-92
    • Takahashi, K.1    Sekiguchi, M.2
  • 4
    • 34250797327 scopus 로고    scopus 로고
    • B. Wunderle, R. Mrossko, O. Wittler, E. Kaulfersch, P. Ramm, B. Michel and H. Reichl, Thermo-Mechanical Reliability of 3D-Integrated Microstructures in Stacked Silicon, Materials Research Society Symposium Proceedings, 970, Warrendale, PA, 2007, 0970-Y02-04.
    • B. Wunderle, R. Mrossko, O. Wittler, E. Kaulfersch, P. Ramm, B. Michel and H. Reichl, "Thermo-Mechanical Reliability of 3D-Integrated Microstructures in Stacked Silicon," Materials Research Society Symposium Proceedings, vol. 970, Warrendale, PA, 2007, 0970-Y02-04.
  • 5
    • 70449092031 scopus 로고    scopus 로고
    • Fammos TX User Guide and Fammos TX Reference Manual, Synopsys, Inc., September 2008.
    • Fammos TX User Guide and Fammos TX Reference Manual, Synopsys, Inc., September 2008.
  • 6
    • 0019916789 scopus 로고
    • A Graphical Representation of the Piezoresistance Coefficients in Silicon
    • January
    • Y. Kanda, "A Graphical Representation of the Piezoresistance Coefficients in Silicon," IEEE Transactions on Electron Devices, vol. ED-29, no. 1, pp. 64-70, January 1982.
    • (1982) IEEE Transactions on Electron Devices , vol.ED-29 , Issue.1 , pp. 64-70
    • Kanda, Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.