Partially Depleted SOI MOSFETs Under Uniaxial Tensile Strain

IEEE Transactions on Electron Devices

Volumn 51, Issue 3, 2004, Pages 317-323

  Zhao, Wei ^a   He, Jianli ^a   Belford, Rona E ^b   Wernersson, Lars Erik ^a   Seabaugh, Alan ^a  

^a University of Notre Dame   (United States)

^b Belford Research Inc   (United States)

Author keywords

Mechanical stress; Mobility enhancement; MOSFET mobility; Partially depleted silicon on insulator (SOI) MOSFET; Strained Si

Indexed keywords

ELECTRIC CURRENT MEASUREMENT; ELECTRON MOBILITY; GATES (TRANSISTOR); HOLE MOBILITY; SILICON ON INSULATOR TECHNOLOGY; STRAIN MEASUREMENT; STRESS ANALYSIS; TENSILE TESTING; THRESHOLD VOLTAGE;

MOBILITY ENHANCEMENT; MOSFET MOBILITY; PARTIALLY DEPLETED SILICON-ON-INSULATOR (SOI) MOSFET; STRAINED-SI;

MOSFET DEVICES;

EID: 1642294881     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.823048     Document Type: Article

References (23)

1. J. Welser, J. L. Hoyt, and J. F. Gibbons, "Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors," IEEE Electron Device Lett., vol. 15, pp. 100-102, Mar. 1994.
2. K. Rim, J. L. Hoyt, and J. F. Gibbons, "Fabrication and analysis of deep submicron strained-Si n-MOSFETs," IEEE Trans. Electron Devices, vol. 47, pp. 1406-1415, July 2000.
3. S. Takagi, N. Sugiyama, T. Mizuno, T. Tezuka, and A. Kurobe, "Device structure and electrical characteristics of strained-Si-on-insulator (strained-SOI) MOSFETs," Mater. Sci. Eng., vol. B89, pp. 426-434, Feb. 2002.
4. T. Mizuno, N. Sugiyama, T. Tezuka, and S. Takagi, "(110) strained-SOI n-MOSFETs with higher electron mobility," IEEE Electron Device Lett., pp. 1-3, Jan. 2003.
5. F. Ootsuka, S. Wakahara, K. Ichinose, A. Honzawa, S. Wada, H. Sato, T. Ando, H. Ohta, K. Watanabe, and T. Onai, "A highly dense, high-performance 130 nm node CMOS technology for large scale system-on-a-chip applications, " in IEDM Tech. Dig., Dec. 2000, pp. 575-578.
6. S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi, "Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design," in IEDM Tech. Dig., Dec., 2000, pp. 247-250.
7. A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, and F. Ootsuka, "Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement," in IEDM Tech. Dig., Dec., 2001, pp. 433-436.
8. K. Ota, K. Sugihara, H. Sayama, T. Uchida, H. Oda, T. Eimori, H. Morimoto, and Y. Inoue, "Novel locally strained channel technique for high performance 55 nm CMOS," in IEDM Tech. Dig., Dec., 2002, pp. 27-30.
9. A. P. Dorey and T. S. Maddern, "The effect of strain on MOS transistors," Solid State Electron., vol. 12, pp. 185-189, Mar. 1969.
10. B. M. Haugerud, L. A. Bosworth, and R. E. Belford, "Mechanically induced strain enhancement of metal-oxide-semiconductor field effect transistors," J. Appl. Phys., vol. 94, pp. 4102-4107, 2003.
11. A. Hamada, T. Furusawa, N. Saito, and E. Takeda, "A new aspect of mechanical stress effects in scaled MOS devices," IEEE Trans. Electron Devices, vol. 38, pp. 895-900, Apr. 1991.
12. R. E. Belford, "Uniaxial tensile-strained Si devices," J. Electron. Mater., vol. 30, no. 7, pp. 807-811, 2001.
13. R. E. Belford, W. Zhao, J. Potashnik, Q. Liu, and A. Seabaugh, "Performance-augmented CMOS using back-end uniaxial strain," in Proc. IEEE 60th Dev. Res. Conf. Dig., June, 2002, pp. 41-42.
14. Y. G. Wang, D. B. Scott, J. Wu, J. L. Waller, J. Hu, K. Liu, and V. Ukraintsev, "Effects of uniaxial mechanical stress on drive current of 0. 13 μm MOSFETs," IEEE Trans. Electron Devices, vol. 50, pp. 529-531, Feb. 2003.
15. A. Lochtefeld and D. A. Antoniadis, "Investigating the relationship between electron mobility and velocity in deep scaled NMOS via mechanical stress," IEEE Electron Device Lett., vol. 22, pp. 591-593, Dec. 2001.
16. G. Dorda, "Piezoresistance in quantized conduction bands in silicon inversion layers," J. Appl. Phys., vol. 42, pp. 2053-2060, 1971.
17. Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User's Guide. Norwell, MA: Kluwer, 1999, p. 93.
18. C. G. Sodini, T. W. Ekstedt, and J. L. Moll, "Charge accumulation and mobility in thin dielectric MOS transistors," Solid State Electron., vol. 25, pp. 833-841, 1982.
19. K. Chen, H. C. Wann, J. Dunster, P. K. Ko, and C. Hu, "MOSFET carrier mobility model based on gate oxide thickness, threshold voltage, and gate voltages," Solid State Electron., vol. 39, pp. 1515-1518, 1996.
20. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFETs: Part I - Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, pp. 2357-2362, Dec. 1994.
21. D. Colman, R. T. Bate, and J. P. Mize, "Mobility anisotropy and piezoresistance in silicon p-type inversion layers," J. Appl. Phys., vol. 39, pp. 1923-1931, 1968.
22. S. Cristoloveanu and S. Li, Electrical Characterization of Silicon-on-Insulator Materials and Devices. Norwell, MA: Kluwer, 1995, p. 254.
23. S. Takagi, "Subband structure engineering for realizing scaled CMOS with high performance and low power consumption," in IEICE Tech. Dig., vol. E85-C, May, 2002, pp. 1064-1072.