HPC-mesh: A homogeneous parallel concentrated mesh for fault-tolerance and energy savings

Proceedings - 2011 7th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, ANCS 2011

Volumn , Issue , 2011, Pages 69-80

  Camacho, Jesús ^a   Flich, José ^a  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

Author keywords

fault tolerance; power consumption; topology

Indexed keywords

CLOCK GATING; EXECUTION TIME; MESH NETWORK; NETWORK INTERFACE; REAL APPLICATIONS; SIMULATED SYSTEM; SUBNETWORKS; TRAFFIC DEMANDS; TRAFFIC RATE; WORKING CONDITIONS;

ALGORITHMS; ELECTRIC POWER UTILIZATION; ENERGY UTILIZATION; FAULT TOLERANCE; NETWORK ARCHITECTURE; TOPOLOGY;

MESH NETWORKING;

EID: 81255129163     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ANCS.2011.17     Document Type: Conference Paper

References (37)

1. J.D. Balfour and W. J. Dally, "Design Tradeoffs for Tiled CMP On-Chip Networks," in Int. Conference on Supercomputing, June 2006.
2. Broadband Engine Processor available at http://en.wikipedia.org/wiki/Cell (microprocessor).
3. J. Camacho, J. Flich, A. Roca and J. Duato, "PC-Mesh: A Dynamic Parallel Concentrated Mesh," accepted in the International Conference on Parallel Processing, September 2011.
4. Everton Carara, Fernando Moraes, And Ney Calazans, "Router architecture for high-performance NoCs," In Proceedings of the 20th annual conference on Integrated circuits and systems design (SBCCI), 2007.
5. Chih-Hao Chao, Kai-Yuan Jheng, Hao-Yu Wang, Jia-Cheng Wu, and An-Yeu Wu, "Traffic- and thermal-aware run-time thermal management scheme for 3D NoC systems," in ACM/IEEE Int. Symp. Networks-on-Chip (NoCS), pp. 223-230, May 2010.
6. X. Chen and L.-S. Peh, "Leakage Power Modeling and Optimization in Interconnection Networks," in Int. Symposium on Low Power Electronics and Design, pages 90-95, August 2003.
7. W. J. Dally, "Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks," in IEEE Transactions on Computers, 40(9):1016-1023, September 1991.
8. B. Grot, J. Hestness, S. Keckler, O. Mutly, "Express Cube Topologies for On-Chip Interconnects," in Int. Symposium on High-Performance Computer Architecture, 2009.
9. K. C. Hale, B. Grot, S. W. Keckler, "Segment Gating for Static Energy Reduction in Networks-on-Chip," in Int. Workshop on Network-on-Chip Architectures, December 2009.
10. Wen-Hsiang Hu, Seugn Eun Lee, and Nader Bagherzadeh, "DMesh: a Diagonally-Linked Mesh Network-on-Chip Architecture", in First Int. Workshop on Network on Chip Architectures Workshop, 2008.
11. Z. Hu, A. Buyuktosunoglu, V. Srinivasan, V. Zyuban, H. Jacobson, and P. Bose, "Microarchitectural Techniques for Power Gating of Execution Units," in Int. Symposium on Low Power Electronics and Design, pages 32-37, August 2004.
12. Andrew Kahng, Bin Li, Li-Shiuan Peh and Kambiz Samadi, "ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration," in Design Automation and Test in Europe (DATE), Nice, France, April 2009.
13. J. Kim, J. Balfour, W. Dally, "Flattened Butterfly Topology for On-chip networks," in Int. Symposium on Microarchitecture, December 2007.
14. Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li, "Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip," in ASP-DAC 2011:357-362, 2011.
15. I. Loi, F. Angiolini, and L. Benini, "Supporting vertical links for 3d networks-on-chip: Toward an automated design and analysis flow," in Proceedings of the Nano-Net Conference, pp. 23-27, 2007.
16. Peter S. Magnusson et al., "Simics: A full system simulation platform," in Computer, 35(2):50-58, 2002.
17. M. Martin, D. Sorin, B. Beckmann, M. Marty, M. Xu, A. Almadeen, K. Moore, M. Hill, D. Wood, "Multifacet, a general execution-driven multiprocessor simulator (GEMS) toolset," in Computer Architecture News, September 2005.
18. H. Matsutani, M. Koibuchi, H. Amano, and D. Wang, "Run-time Power Gating of On-Chip Switches Using Look-Ahead Routing.," in Asia and South Pacific Design Automation Conference, pages 55-60, January 2008.
19. H. Matsutani, M. Koibuchi, D. Wang, and H. Amano, "Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks," in Int. Symposium on Networks-on-Chip, pages 23-32, April 2008.
20. Seongmin Noh; Vu-Duc Ngo; Haiyan Jao; Hae-Wook Choi, "Multiplane Virtual Channel Router for Network-on-Chip Design", in First International Conference on Communications and Electronics (ICCE), 2006.
21. S. Pasricha, "Exploring serial vertical interconnects for 3D ICs," in Proceedings of the 46th Annual Design Automation Conference, pp. 581-586, ACM, 2009.
22. V. F. Pavlidis and E. G. Friedman, "3-D Topologies for Networks-on-Chip," in IEEE TVLSI, October 2007.
23. D. Pham et al., "Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor," in IEEE Journal of Solid-State Circuits, 41(1):179-196, January 2006.
24. M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar, "Gated-Vdd: a Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories,"in Int. Symposium on Low Power Electronics and Design, pages 90-95, July 2000.
25. A. Pullini et al., "Bringing NoCs to 65nm,"in IEEE Micro Magazine, Vol. 12, Nr. 5, pp. 75-85, IEEE Press, September 2007.
26. Single-chip Cloud Computer available at http://techresearch.intel.com/ articles/Tera- Scale/1826.htm.
27. V. Soteriou and L.-S. Peh, "Dynamic Power Management for Power Optimization of Interconnection Networks Using On/Off Links," in Int. Symposium on High Performance Interconnects, pages 15-20, August 2003.
28. Teraflops Research Chip available at http://www.intel.com/pressroom/kits/ teraflops.
29. Tile-Gx Processors Family available at http://www.tilera.com/products/ TILE-Gx.php.
30. S. Vangal et al., "An 80-Tile 1.28 TFLOPS Network-on-Chip in 65nm CMOS," in Int. Solid-State Circuits Conference, pages 98-99, February 2007.
31. E. Waingold et al., "Baring It All to Software: RAWMachines," in IEEE Computer, 30(9):86-93, September 1997.
32. Weerasekera, Roshan and Zheng, Li-Rong and Pamunuwa, Dinesh B. and Tenhunen, Hannu, "Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs," in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, pp. 212-219, 2007.
33. D. Wentzlaff et al., "On-Chip Interconnection Architecture of the Tile Processor," in IEEE Micro, 27(5):15-31, September/October 2007.
34. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, A. Gupta, A., "The SPLASH-2 programs: characterization and methodological considerations," in 22nd Annual Int. Symposium on Computer Architecture, Italy, June 22 - 24, pp. 24-36, 1995.
35. T. C. Xu, P. Liljeberg, and H. Tenhunen, "A study of through silicon via impact to 3d network-on-chip design," in Proceedings of the 2010 International Conference on Electronics and Information Engineering (ICEIE 2010), August 2010.
36. C. Zhu, Z. Gu, L. Shang, R. Dick, and R. Joseph, "Three-dimensional chip-multiprocessor run-time thermal management," in IEEE Transactions on Computer-Aided Design, vol. 27, no.3, 2008.
37. A.E. Zonouz et al. "A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction," in 2009 Euromicro Conference on Digital System Design, 1999.