A fault tolerant NoC architecture for reliability improvement and latency reduction

12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009

Volumn , Issue , 2009, Pages 473-480

  Zonouz, A Ehsani ^a   Seyrafi, M ^a   Asad, A ^a   Soryani, M ^a   Fathy, M ^a   Berangi, R ^a  

^a IRAN UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Iran)

Author keywords

Fault tolerance; Network on chip; Perfomance metric; Reliability

Indexed keywords

CHIP DESIGN; COST-SENSITIVE; FAULT-TOLERANT; FAULTY SWITCHES; FEATURE SIZES; LATENCY REDUCTION; NETWORK ON CHIP; NOC ARCHITECTURES; PERFOMANCE METRIC; PROPOSED ARCHITECTURES; RELIABILITY IMPROVEMENT; SINGLE CHIPS;

COMPUTATION THEORY; DESIGN; ELECTRIC NETWORK TOPOLOGY; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; REDUNDANCY;

QUALITY ASSURANCE;

EID: 74549189077     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2009.170     Document Type: Conference Paper

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