Traffic- and thermal-aware run-time thermal management scheme for 3D NoC systems

NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2010, Pages 223-230

  Chao, Chih Hao ^a   Jheng, Kai Yuan ^a   Wang, Hao Yu ^a   Wu, Jia Cheng ^a   Wu, An Yeu ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

3D IC; 3D NoC; Routing; Run time thermal management; Thermal aware; Throttling; Traffic aware

Indexed keywords

CHIP TEMPERATURE; HIGH TEMPERATURE; HIGHER NETWORKS; IC TECHNOLOGY; LOWER-POWER CONSUMPTION; MAPPING TECHNIQUES; PER UNIT; PERFORMANCE IMPACT; POWER DENSITIES; RUNTIMES; TEMPERATURE REGULATIONS; THERMAL IMPACTS; THERMAL MANAGEMENT; THERMAL SAFETY; THREE-DIMENSIONAL NETWORKS;

DIES; MICROPROCESSOR CHIPS; TEMPERATURE CONTROL; THREE DIMENSIONAL; VLSI CIRCUITS;

ROUTERS;

EID: 77955112291     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2010.32     Document Type: Conference Paper

References (15)

1. L. Benini and G. De Micheli, "Networks on chip: a new paradigm for systems on chip design," Proc. Proc. IEEE Conference on Design, Automation, and Test in Europe (DATE'02), Mar. 2002, pp. 418-419.
2. A. W. Topol et al., "Three-dimensional integrated circuits," IBM J. Research Development, pp. 491-506, Jul. 2006.
3. B. Black et al., "Die Stacking (3D) Microarchitecture," in Proc. IEEE/ACM International Symposium on Microarchitecture (Micro'06), Dec. 2006.
4. V. Pavlidis and E. Friedman, "3-D Topologies for Networks-on-Chip," IEEE Trans. Very Large Scale Integration Systems, vol. 15, no. 10, pp. 1081-1090, Oct. 2007. (Pubitemid 47460369)
5. D. Park et al., "MIRA: A Multi-Layered On-Chip Interconnect Router Architecture," in Proc. Intl. Symp. Computer Architecture (ISCA'08), pp.251-261, June 2008.
6. C. Zhu, Z. Gu, L. Shang, R. P. Dick, and R. Joseph, "Three- Dimensional Chip-Multiprocessor Run-Time Thermal Management," IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1479-1492, Aug. 2008.
7. L. Shang, L. Peh, A. Kumar, and N. K. Jha, "Thermal modeling, characterization and management of on-chip networks," in Proc. IEEE/ACM International Symposium on Microarchitecture (Micro'04), Dec. 2004, pp. 67-78.
8. Y. Hoskote, S. Vangal, A. Singh, N. Borkar, and S. Borkar," A 5-GHz Mesh Interconnect for A Teraflops Processor", IEEE MICRO, vol. 27, pp. 51-61, 2007.
9. K. Puttaswamy and G. H. Loh, "Thermal herding: microarchitecture techniques for controlling hotspots in high-performance 3D-integrated processors," in Proc. IEEE High Performance Computer Architecture (HPCA), Feb. 2007, pp. 193-204.
10. W. Huang et al., "HotSpot: A compact thermal modeling methodology for early-stage VLSI design," IEEE Trans. Very Large Scale Integration Systems, vol. 14, no. 5, pp.501-513, May 2006.
11. Noxim: network-on-chip simulator [Online]. Available: http://sourceforge.net/projects/noxim/.
12. CFD-RC [Online]. Available: http://www.cfdrc.com/.
13. H. Matsutani, M. Koibuchi, and H. Amano, "Tightly-Coupled Multi- Layer Topologies for 3D NoCs," in International Conference on Parallel Processing (ICPP), pp. 75-85, 2007.
14. J. Kim et al., "A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures," in Proc. Intl. Symp. Computer Architecture (ISCA'07), June 2007, pp.138-149.
15. K.-Y. Jheng, C.-H. Chao, H.-Y. Wang, and A.-Y. Wu, "Traffic-Thermal Mutual-Coupling Co-Simulation Platform for Three-Dimensional Network-on-Chip," in Proc. IEEE Intl. Symp. on VLSI Design, Automation, and Test (VLSI-DAT'10), Apr. 2010.