Vertical interconnects squeezing in symmetric 3D mesh network-on-chip

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2011, Pages 357-362

  Liu, Cheng ^a   Zhang, Lei ^a   Han, Yinhe ^a   Li, Xiaowei ^a  

^a INSTITUTE OF COMPUTING TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATED CIRCUIT; 3-D INTEGRATION; 3D MESHES; CHIP AREAS; DESIGN CHALLENGES; NETWORK ON CHIP; ON CHIP INTERCONNECT; PLANAR LAYERS; RESEARCH EFFORTS; ROUTING CONGESTION; SCALING PROBLEM; THREE DIMENSIONAL (3D) INTEGRATION; TIME DIVISION; VERTICAL CHANNELS;

COMPUTER AIDED DESIGN; INTEGRATION; SERVERS; THREE DIMENSIONAL; TIME DIVISION MULTIPLE ACCESS; VLSI CIRCUITS;

ROUTERS;

EID: 79952915826     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2011.5722213     Document Type: Conference Paper

References (25)

1. W. Dally and B. Towles, "Route packets, not wires: on-chip interconnection networks," in Design Automation Conference, 2001. Proceedings, pp. 684-689, 2001.
2. L. Benini and G. De Micheli, "Networks on chips: A new SoC paradigm," Computer, vol. 35, no. 1, pp. 70-78, 2002.
3. K. Bernstein, "New Dimensions in Performance," System, vol. 2002, no. 2004, p. 2006, 2000.
4. T. Vucurevich, "The Long Road to 3-D Integration: Are We There Yet," in Keynote speech at the 3D Architecture Conference, 2007.
5. G. Loh, Y. Xie, and B. Black, "Processor design in 3D die-stacking technologies," IEEE Micro, vol. 27, no. 3, pp. 31-48, 2007.
6. Y. Xie, G. Loh, B. Black, and K. Bernstein, "Design space exploration for 3D architectures," ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 2, no. 2, pp. 65-103, 2006.
7. B. Feero and P. Pande, "Performance evaluation for three-dimensional networks-on-chip," in IEEE Computer Society Annual Symposium on VLSI, 2007. ISVLSI'07, pp. 305-310, 2007.
8. I. Loi, F. Angiolini, and L. Benini, "Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow," in Proceedings of the 2nd international conference on Nano-Networks, p. 15, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), 2007.
9. F. Li, C. Nicopoulos, T. Richardson, Y. Xie, V. Narayanan, and M. Kandemir, "Design and management of 3D chip multiprocessors using network-in-memory," ACM SIGARCH Computer Architecture News, vol. 34, no. 2, p. 141, 2006.
10. J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie, V. Narayanan, M. Yousif, and C. Das, "A novel dimensionally-decomposed router for on-chip communication in 3D architectures," ACM SIGARCH Computer Architecture News, vol. 35, no. 2, p. 149, 2007.
11. I. Loi, S. Mitra, T. Lee, S. Fujita, and L. Benini, "A low-overhead fault tolerance scheme for TSV-based 3D network on chip links," in Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, pp. 598-602, IEEE Press, 2008.
12. D. Park, S. Eachempati, R. Das, A. Mishra, Y. Xie, N. Vijaykrishnan, and C. Das, "MIRA: A multi-layered on-chip interconnect router architecture," in Proceedings of the 35th International Symposium on Computer Architecture, pp. 251-261, IEEE Computer Society, 2008.
13. V. Pavlidis and E. Friedman, "3-D topologies for networks-on-chip," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 10, pp. 1081-1090, 2007.
14. Y. Xu, Y. Du, B. Zhao, X. Zhou, Y. Zhang, and J. Yang, "A low-radix and low-diameter 3D interconnection network design,"
15. A. Topol et al., "Three-dimensional integrated circuits," IBM Journal of Research and Development, vol. 50, no. 4/5, p. 506, 2006.
16. K. Bernstein, P. Andry, J. Cann, P. Emma, D. Greenberg, W. Haensch, M. Ignatowski, S. Koester, J. Magerlein, R. Puri, et al., "Interconnects in the third dimension: Design challenges for 3D ICs," in Proceedings of the 44th annual Design Automation Conference, p. 567, ACM, 2007.
17. R. Patti, "Three-dimensional integrated circuits and the future of system-on-chip designs," Proceedings of the IEEE, vol. 94, no. 6, 2006.
18. S. Pasricha, "Exploring serial vertical interconnects for 3D ICs," in Proceedings of the 46th Annual Design Automation Conference, pp. 581-586, ACM, 2009.
19. H. Sangki, "3D Super-Via for Memory Applications,"
20. S. Das, A. Fan, K. Chen, C. Tan, N. Checka, and R. Reif, "Technology, performance, and computer-aided design of three-dimensional integrated circuits," in Proceedings of the 2004 international symposium on Physical design, p. 115, ACM, 2004.
21. C. Ababei, Y. Feng, B. Goplen, H. Mogal, T. Zhang, K. Bazargan, and S. Sapatnekar, "Placement and routing in 3D integrated circuits,"
22. B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, B. Eyckens, S. Stoukatch, D. Tezcan, Z. Tokei, et al., "3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10¿ m pitch through-Si vias," in Electron Devices Meeting, 2006. IEDM'06. International, pp. 1-4, 2006.
23. R. Mullins, A. West, and S. Moore, "Low-latency virtual-channel routers for on-chip networks," in Proceedings of the 31st annual international symposium on Computer architecture, IEEE Computer Society Washington, DC, USA, 2004.
24. R. Mullins, A. West, and S. Moore, "The design and implementation of a low-latency on-chip network," in Proceedings of the 2006 Asia and South Pacific Design Automation Conference, p. 169, IEEE Press, 2006.
25. S. Inc, "Design compiler," Online, http://www. synopsys. com, 2009.