Electrical impact of line-edge roughness on sub-45-nm node standard cells

Journal of Micro/Nanolithography, MEMS, and MOEMS

Volumn 9, Issue 4, 2010, Pages

  Ban, Yongchan ^a   Sundareswaran, Savithri ^b   Pan, David Z ^a  

^a The University of Texas at Austin   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

Characterization; Circuit performance; Design for manufacturing; Line edge roughness; Lithography variation; Standard cell

Indexed keywords

DEGRADATION; ELECTRIC BATTERIES; ELECTRIC NETWORK ANALYSIS; LEAKAGE CURRENTS; STANDARDS; VLSI CIRCUITS;

CELL CHARACTERIZATION; CIRCUIT PERFORMANCE; CRITICAL PROBLEMS; DESIGN FOR MANUFACTURING; DEVICE PARAMETERS; ETCH SIMULATION; GATE LENGTH; LEAKAGE CURRENT DEGRADATION; LINE EDGE ROUGHNESS; LINE ENDS; PERFORMANCE LIMITATIONS; ROOT MEAN SQUARE VALUES; SATURATION CURRENT; STANDARD CELL; VERY-LARGE-SCALE INTEGRATION CIRCUITS; WORST CASE;

ROUGHNESS MEASUREMENT;

EID: 80052648730     PISSN: 19325150     EISSN: 19325134     Source Type: Journal    
DOI: 10.1117/1.3500746     Document Type: Conference Paper

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