Total sensitivity based DFM optimization of standard library cells

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2010, Pages 113-120

  Ban, Yongchan ^a   Sundareswaran, Savithri ^b   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

DFM; Lithography; Optimization; Sensitivity; VLSI

Indexed keywords

45NM NODE; BUILDING BLOCKES; CIRCUIT PERFORMANCE; DELAY VARIATION; EARLY DESIGN STAGES; FIRST-ORDER MODELS; FUNDAMENTAL CIRCUITS; LAYOUT OPTIMIZATION; LITHOGRAPHY OPTIMIZATION; PROCESS CONDITION; PROCESS VARIATION; STANDARD CELL; STANDARD LIBRARIES;

DESIGN; ELECTRIC BATTERIES; OPTIMIZATION; STANDARDS; TIME DELAY;

SENSITIVITY ANALYSIS;

EID: 77952259174     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1735023.1735053     Document Type: Conference Paper

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