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Volumn , Issue , 2008, Pages 286-291

A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; INTEGRATED CIRCUIT LAYOUT; PARAMETER EXTRACTION; THRESHOLD VOLTAGE; TRANSISTORS;

EID: 57849148539     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681587     Document Type: Conference Paper
Times cited : (10)

References (16)
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  • 2
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    • Impact of Subwavelength CD Tolerance on Device Performance
    • A. Balasinski, L. Karklin, and V. Axelrad, "Impact of Subwavelength CD Tolerance on Device Performance," in Proc. SPIE, vol. 4692, pp. 361-368, 2002.
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    • Balasinski, A.1    Karklin, L.2    Axelrad, V.3
  • 5
    • 2642552225 scopus 로고    scopus 로고
    • TCAD-Based Statistical Analysis and Modeling of Gate Line-Edge Roughness Effect on Nanoscale MOS Transistor Performance and Scaling
    • S. D. Kim, H. Wada, and J. C. S. Woo, "TCAD-Based Statistical Analysis and Modeling of Gate Line-Edge Roughness Effect on Nanoscale MOS Transistor Performance and Scaling," IEEE Trans on Semiconductor Manufacturing, vol.17, no.2, 2004.
    • (2004) IEEE Trans on Semiconductor Manufacturing , vol.17 , Issue.2
    • Kim, S.D.1    Wada, H.2    Woo, J.C.S.3
  • 8
    • 25144468812 scopus 로고    scopus 로고
    • A Novel Design-Process Optimization Technique Based on Self-Consistent Electrical Performance Evaluation
    • V. Axelrad, A. Shibkov, G. Hill, H. J. Lin, C. Tabery, D. White, V. Boksha, and R. Thilmany, "A Novel Design-Process Optimization Technique Based on Self-Consistent Electrical Performance Evaluation," in Proc. SPIE, vol. 5756, pp. 419-426, 2005.
    • (2005) Proc. SPIE , vol.5756 , pp. 419-426
    • Axelrad, V.1    Shibkov, A.2    Hill, G.3    Lin, H.J.4    Tabery, C.5    White, D.6    Boksha, V.7    Thilmany, R.8
  • 9
    • 33745608353 scopus 로고    scopus 로고
    • From Poly Line to Transistor: Building BSIM Models for Non-Rectangular Transistors
    • W. J. Poppe, L. Capodieci, J. Wu, and A. Neureuther, "From Poly Line to Transistor: Building BSIM Models for Non-Rectangular Transistors," in Proc. SPIE, vol.6156, 2006.
    • (2006) Proc. SPIE , vol.6156
    • Poppe, W.J.1    Capodieci, L.2    Wu, J.3    Neureuther, A.4
  • 10
    • 33745798166 scopus 로고    scopus 로고
    • Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis
    • P. Gupta, A. Kahng, Y. Kim, S. Shah, and D. Sylvester, "Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis," in Proc. SPIE, vol.6156, 2006.
    • (2006) Proc. SPIE , vol.6156
    • Gupta, P.1    Kahng, A.2    Kim, Y.3    Shah, S.4    Sylvester, D.5
  • 11
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    • Standard Cell Characterization Considering Lithography Induced Variations
    • K. Cao, S. Dobre, and J. Hu, "Standard Cell Characterization Considering Lithography Induced Variations," in Proc. Design Automation Conf., pp. 801-804, 2006.
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    • Cao, K.1    Dobre, S.2    Hu, J.3
  • 12
    • 40349106622 scopus 로고    scopus 로고
    • A Unified Non-Rectangular Device and Circuit Simulation Model for Timing and Power
    • S. X. Shi, P. Yu, and D. Z. Pan, "A Unified Non-Rectangular Device and Circuit Simulation Model for Timing and Power," in Proc. International Conf. on Computer-Aid Design, pp. 423-428, 2006.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.