Impact of line width roughness on Intel's 65 nm process devices

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6519, Issue PART 1, 2007, Pages

  Chandhok, Manish ^a   Datta, Suman ^a   Lionberger, Daniel ^a   Vesecky, Scott ^a  

^a INTEL CORPORATION   (United States)

Author keywords

65 nm process; CD; Device performance; LER; Line edge roughness; LWR; Metrology

Indexed keywords

DEVICE PERFORMANCE; FINAL CHECK CRITICAL DIMENSION (FCCD); INCREASES OFF-CURRENT (IOFF),; LINE EDGE ROUGHNESS;

DEGRADATION; GATE DIELECTRICS; IONS; RANDOM VARIABLES; SHRINKAGE; SURFACE ROUGHNESS;

MOS DEVICES;

EID: 35148900275     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.712955     Document Type: Conference Paper

References (5)

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