Effective robustness analysis using bounded model checking techniques

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 30, Issue 8, 2011, Pages 1239-1252

  Fey, Górschwin ^a   Sulflow, André ^a   Frehse, Sütefan ^a   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

Author keywords

Fault tolerance; formal verification; SAT

Indexed keywords

BOUNDED MODEL CHECKING; ENVIRONMENTAL RADIATION; FAULT-DETECTION MECHANISMS; FORMAL MODEL; FORMAL VERIFICATIONS; ROBUSTNESS ANALYSIS; SAT; SHRINKING FEATURE SIZES; TRANSIENT FAULTS; UPPER BOUND; VERIFICATION PROBLEMS;

FAULT DETECTION; FORMAL METHODS; MODEL CHECKING;

FAULT TOLERANCE;

EID: 79960692783     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2011.2120950     Document Type: Article

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