메뉴 건너뛰기




Volumn 2005, Issue , 2005, Pages 550-555

Deployment of Better Than Worst-Case Design: Solutions and needs

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSORS; RELIABILITY BUDGETS; RELIABLE CHECKER MECHANISMS; SILICON FABRICATION;

EID: 33748571467     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2005.43     Document Type: Conference Paper
Times cited : (18)

References (28)
  • 2
    • 0034510791 scopus 로고    scopus 로고
    • Logic design validation via simulation and automatic test pattern generation
    • H. Al-Asaad and J. P. Hayes. Logic design validation via simulation and automatic test pattern generation. Journal of Electronic Testing, 16(6):575-589, 2000.
    • (2000) Journal of Electronic Testing , vol.16 , Issue.6 , pp. 575-589
    • Al-Asaad, H.1    Hayes, J.P.2
  • 6
    • 1842582489 scopus 로고    scopus 로고
    • Making typical silicon matter with Razor
    • T. Austin, D. Blaauw, T. Mudge, and K. Flautner. Making typical silicon matter with Razor. IEEE Computer, 37(3):57-65, 2004.
    • (2004) IEEE Computer , vol.37 , Issue.3 , pp. 57-65
    • Austin, T.1    Blaauw, D.2    Mudge, T.3    Flautner, K.4
  • 19
    • 0030291568 scopus 로고    scopus 로고
    • Testing ICs: Getting to the core of the problem
    • B. T. Murray and J. P. Hayes. Testing ICs: Getting to the core of the problem. IEEE Computer, 29(11):32-38, 1996.
    • (1996) IEEE Computer , vol.29 , Issue.11 , pp. 32-38
    • Murray, B.T.1    Hayes, J.P.2
  • 23
    • 0036508455 scopus 로고    scopus 로고
    • Reliability limits for the gate insulator in CMOS technology
    • J. H. Stathis. Reliability limits for the gate insulator in CMOS technology. IBM Journal of Research and Development, 46(2/3):265-286, 2002.
    • (2002) IBM Journal of Research and Development , vol.46 , Issue.2-3 , pp. 265-286
    • Stathis, J.H.1
  • 24
    • 24544451157 scopus 로고    scopus 로고
    • Achieving typical delays in synchronous systems via timing error toleration
    • University of Rhode Island, Mar.
    • A. Uht. Achieving typical delays in synchronous systems via timing error toleration. Technical Report TR-032000-0100, University of Rhode Island, Mar. 2000.
    • (2000) Technical Report , vol.TR-032000-0100
    • Uht, A.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.