Integration of learning techniques into incremental satisfiability for efficient path-delay fault test generation

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 1002-1007

  Chandrasekar, Kameshwar ^a   Hsiao, Michael S ^a  

^a Virginia Polytechnic Institute and State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUITS; BOOLEAN SATISFIABILITY; PATH DELAY FAULT (PDF) MODEL;

DELAY CONTROL SYSTEMS; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; PROBLEM SOLVING;

LEARNING SYSTEMS;

EID: 33646903261     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.187     Document Type: Conference Paper

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