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Volumn , Issue , 2009, Pages 190-195

Computing bounds for fault tolerance using formal techniques

Author keywords

Fault tolerance; Formal verification; SAT

Indexed keywords

COMPUTER AIDED DESIGN; FAULT DETECTION; FORMAL METHODS; FORMAL VERIFICATION;

EID: 70350743260     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1629911.1629963     Document Type: Conference Paper
Times cited : (18)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.