Reusing learned information in SAT-based ATPG

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 69-74

  Fey, Görschwin ^a   Warode, Tim ^a   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING LANGUAGES; INTEGRATED CIRCUITS; LEARNING ALGORITHMS; NETWORKS (CIRCUITS);

INDUSTRIAL CIRCUITS; LEARNING TECHNIQUES;

EMBEDDED SYSTEMS;

EID: 34548850252     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.137     Document Type: Conference Paper

References (18)

1. K. Chandrasekar and M. S. Hsiao. Integration of learning techniques into incremental satisfiability for efficient pathdelay fault test generation. In Design, Automation and Test in Europe, pages 1002-1007, 2005.
2. M. Davis, G. Logeman, and D. Loveland. A machine program for theorem proving. Comm. of the ACM, 5:394-397, 1962.
3. R. Drechsler and G. Fey. Automatic test pattern generation. In Formal Methods for Hardware Verification, LNCS, pages 30-55, 2006.
4. N. Eén and N. Sörensson. An extensible SAT solver. In SAT 2003, volume 2919 of LNCS, pages 502-518, 2004.
5. H. Fujiwara and T. Shimono. On the acceleration of test generation algorithms. IEEE Trans. on Comp., 32:1137-1144, 1983.
6. P. Goel. An implicit enumeration algorithm to generate tests for combinational logic. IEEE Trans. on Comp., 30:215-222, 1981.
7. D. Große and R. Drechsler. Acceleration of SAT-based iterative property checking. In CHARME, volume 3725 of LNCS, pages 349-353. Springer, 2005.
8. W. Kunz. HANNIBAL: An efficient tool for logic verification based on recursive learning. In Int'l Conf. on CAD, pages 538-543, 1993.
9. T. Larrabee. Test pattern generation using Boolean satisfiability. IEEE Trans. on CAD, 11:4-15, 1992.
10. J. Marques-Silva and K. Sakallah. GRASP: A search algorithm for propositional satisfiability. IEEE Trans, on Comp., 48(5):506-521, 1999.
11. M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Design Automation Conf., pages 530-535, 2001.
12. M. Schulz, E. Trischler, and T. Sarfert. SOCRATES: A highly efficient automatic test pattern generation system. In Int'l Test Conf., pages 1016-1026, 1987.
13. J. Shi, G. Fey, R. Drechsler, A. Glowatz, F. Hapke, and J. Schlöffel. PASSAT: Effcient SAT-based test pattern generation for industrial circuits. In IEEE Annual Symposium on VLSI, pages 212-217, 2005.
14. J. Shi, G. Fey, R. Drechsler, A. Glowatz, J. Schlöffel, and F. Hapke. Experimental studies on SAT-based test pattern generation for industrial circuits. In Int'l Conf. on ASIC, pages 967-970, 2005.
15. O. Shtrichman. Pruning techniques for the SAT-based bounded model checking problem. In CHARME, volume 2144 of LNCS, pages 58-70, 2001.
16. P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. Combinational test generation using satisfiability. IEEE Trans, on CAD, 15:1167-1176, 1996.
17. T. Warode. Strukturelles Lernen in der erfüllbarkeitsbasierten Testmustergenerierung (Structural learning for test pattern generation based on satisfiability). Master's thesis, University of Bremen, 2006.
18. J. Whittemore, J. Kim, and K. Sakallah. SATIRE: A new incremental satisfiability engine. In Design Automation Conf., pages 542-545, 2001.