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Volumn 2005, Issue , 2005, Pages 260-265

A new approach for early dependability evaluation based on formal property checking and controlled mutations

Author keywords

[No Author keywords available]

Indexed keywords

FAULT TOLERANT COMPUTER SYSTEMS; IDENTIFICATION (CONTROL SYSTEMS); MATHEMATICAL MODELS; PROBABILITY;

EID: 33745497169     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2005.8     Document Type: Conference Paper
Times cited : (37)

References (17)
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    • Leveugle, R.1    Hadjiat, K.2
  • 5
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    • R. Leveugle, "Early analysis of fault-attack effects for cryptographic hardware", Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Florence, Italy, June 30, 2004, Supplemental volume of the 2004 International Conference on Dependable Systems and Networks (DSN), 2004, pp. 348-353
    • (2004) Supplemental Volume of the 2004 International Conference on Dependable Systems and Networks (DSN) , pp. 348-353
    • Leveugle, R.1
  • 7
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    • Accurate and efficient analysis of single event transients in VLSI circuits
    • Kos, Greece, July 7-9
    • M. Sonza-Reorda, M. Violante, "Accurate and efficient analysis of single event transients in VLSI circuits", 9th IEEE International On-Line Testing symposium, Kos, Greece, July 7-9, 2003, pp. 101-105
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    • Sonza-Reorda, M.1    Violante, M.2
  • 8
    • 0027594398 scopus 로고
    • Formal verification of sequential hardware: A tutorial
    • May
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  • 9
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    • Success-driven learning in ATPG for preimage computation
    • November-December
    • S. Sheng, M. S. Hsiao, "Success-driven learning in ATPG for preimage computation", IEEE Design & Test of Computers, vol. 21, no. 6, November-December 2004, pp.504-512
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    • Sheng, S.1    Hsiao, M.S.2
  • 10
    • 0022769976 scopus 로고
    • Graph-based algorithms for Boolean function manipulation
    • August
    • R. E. Bryant, "Graph-based algorithms for Boolean function manipulation", IEEE transactions on Computers, vol. 35, no. 8, August 1986, pp. 677-691
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    • Bryant, R.E.1
  • 12
    • 70350787997 scopus 로고    scopus 로고
    • Checking safety properties using induction and a SAT-solver
    • 3rd Int. Conf. on Formal Methods in Computer-Aided Design (FMCAD), Austin, TX, USA, November 2000, published in
    • M. Sheeran, S. Singh, G. Stilmarek, "Checking Safety Properties Using Induction and a SAT-Solver", 3rd Int. Conf. on Formal Methods in Computer-Aided Design (FMCAD), Austin, TX, USA, November 2000, published in Lecture Notes in Computer Science, Vol. 1954, 2000, pp. 108-125
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    • Sheeran, M.1    Singh, S.2    Stilmarek, G.3
  • 13
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    • Accelerating bounded model checking of safety properties
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  • 14
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  • 17
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.