On acceleration of SAT-based ATPG for industrial designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 27, Issue 7, 2008, Pages 1329-1333

  Drechsler, Rolf ^a   Eggersglüß, Stephan ^a   Fey, Görschwin ^a   Glowatz, Andreas ^b   Hapke, Friedrich ^b   Schloeffel, Juergen ^b   Tille, Daniel ^a  

^a UNIVERSITY OF BREMEN   (Germany)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

Automatic test pattern generation (ATPG); Boolean satisfiability (SAT); Formal methods; Testing

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; BOOLEAN ALGEBRA; INDUSTRIAL ENGINEERING; INTEGRATED CIRCUITS; MATHEMATICAL TRANSFORMATIONS; NETWORKS (CIRCUITS);

(E ,3E) PROCESS; AUTOMATIC TEST-PATTERN GENERATION (ATPG); BOOLEAN SAT SOLVERS; BOOLEAN SATISFIABILITY (SAT); CLASSICAL ALGORITHMS; CONJUNCTIVE NORMAL FORM (CNF); EXPERIMENTAL RESULTS; INDUSTRIAL DESIGNS; OVERALL PERFORMANCE; PROBLEM INSTANCES; RELEVANT INFORMATION; RUN TIME; STRUCTURAL KNOWLEDGE;

BOOLEAN FUNCTIONS;

EID: 45849085783     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.923107     Document Type: Article

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